x86/icelake/icl-metrics.json

4         "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
11         "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
18         "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25         "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32         "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39         "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46         "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
53         "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
60         "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
73         "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
93 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
110 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
116 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
121 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
127         "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
132 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
150 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
159 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
164         "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
168 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
173 …"MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.…
191 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
192         "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
197 …-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in s…
201 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
207 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
211 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
212 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
216 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
231 …o_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread…
240         "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
253 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
258 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLE…
262 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
266 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
271 …-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and…
280 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
294         "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
304 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma…
309 …he CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB mi…
314         "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
318 …t are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the n…
322 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
327 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
336 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
340 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
345 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
349 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
354 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
358 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
363 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
367 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
372 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
376 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
381 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
387 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
392 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
396 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
397 …"MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0…
402 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
415 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
420 …"PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative …
423 …"BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lowe…
451 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
464 …      "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
471 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
478 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
485 …      "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
487 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
493 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
498 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
501 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
507 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
510 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
516 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
519 …BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code foo…
527 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
532 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
535 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
540 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
543 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
548 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
551 …     "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
556 …on": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound w…
559 …tal pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not…
561 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
567         "BriefDescription": "Total pipeline cost of irregular execution (e.g",
572 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
575 …"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-s…
581 …"PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-…
584 …"BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data trans…
585 …t_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (…
589 …"PublicDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data tran…
592         "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
594 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
598 …"PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related met…
601         "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
602 …"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tm…
606 …pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core B…
609 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
610 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
622         "BriefDescription": "Fraction of branches that are non-taken conditionals",
635 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
641 …"MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_call…
652         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
670 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
674 …-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
677 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
691 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
697         "BriefDescription": "Average number of Uops issued by front-end when it issued something",
709 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
761 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
766 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
769 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
774 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
777 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
782 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
785 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
790 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
793 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
798 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
863 … level TLB) code speculative misses per kilo instruction (misses of any page-size that complete th…
869         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
875         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
881         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
887         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
899 … instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
905 …      "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
911         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
929         "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
935         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
954 …"MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.AL…
971         "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
977         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
983         "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
989         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1043 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1049 …l TLB) data load speculative misses per kilo instruction (misses of any page-size that complete th…
1061         "BriefDescription": "Un-cacheable retired load per kilo instruction",
1067 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
1071 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1081 … TLB) data store speculative misses per kilo instruction (misses of any page-size that complete th…
1087 … level TLB) code speculative misses per kilo instruction (misses of any page-size that complete th…
1093 …l TLB) data load speculative misses per kilo instruction (misses of any page-size that complete th…
1106 … TLB) data store speculative misses per kilo instruction (misses of any page-size that complete th…
1112         "BriefDescription": "Un-cacheable retired load per kilo instruction",
1118 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
1185 …egate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
1208 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for ba…
1212 …s running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX…
1215 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1220 … running with power-delivery for license level 1.  This includes high current AVX 256-bit instruct…
1223 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1228 …e the core was running with power-delivery for license level 2 (introduced in SKX).  This includes…
1232 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_…
1249 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1261         "BriefDescription": "The ratio of Executed- by Issued-Uops",
1265 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
1274 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1280 …    "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
1310 …"MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thr…
1314 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
1319 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1323 …e L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access…
1329 …1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL…
1339 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_c…
1365 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1366         "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
1371 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1384 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1385         "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1392 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1402 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1411         "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_core_clks / 2",
1415 …ly does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be…
1420         "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
1425 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1429 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1434 …- DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic i…
1438 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1439 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1443 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1453 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1457 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1485         "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
1489 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
1494 …"MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / tma_info_thread…
1501 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1506 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1515 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
1524 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
1528 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1530 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_in…
1534 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1538 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
1539 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
1547 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
1590 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1591 … tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALL…
1595 …-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1604 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
1613 …-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
1622 …cal Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options…
1637 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
1642 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
1646 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
1651 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
1664 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1669 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1679 …resents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granu…
1683 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1688 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1692 … CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1697 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
1707 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1712 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
1716 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
1729 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
1730         "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
1750 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…
1773         "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
1780         "MetricExpr": "(cycles\\-t / el\\-start if has_event(el\\-start) else 0)",
1787         "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
1794         "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",