Lines Matching full:cycles
318 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
328 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
332 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt…
345 "BriefDescription": "Reference cycles when the core is not in halt state.",
348 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h…
353 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
357 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
363 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
367 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt…
372 "BriefDescription": "Core cycles when the thread is not in halt state.",
375 …"PublicDescription": "This event counts the number of thread cycles while the thread is not in a h…
381 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat…
388 "BriefDescription": "Thread cycles when thread is not in halt state",
392 …"PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. …
397 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat…
404 "BriefDescription": "Cycles with pending L1 cache miss loads.",
409 … "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.",
414 "BriefDescription": "Cycles with pending L2 cache miss loads.",
420 "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.",
425 "BriefDescription": "Cycles with pending memory loads.",
430 "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.",
440 …"PublicDescription": "This event counts cycles during which no instructions were executed in the e…
471 …"PublicDescription": "This event counts cycles during which no instructions were executed in the e…
476 "BriefDescription": "Stall cycles because IQ is full",
480 "PublicDescription": "Stall cycles due to IQ is full.",
489 …"PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with…
532 …"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear even…
537 …"PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an…
543 …"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear even…
548 …"PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear eve…
598 "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
607 "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
635 …"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nuke…
638 "EventName": "MACHINE_CLEARS.CYCLES",
687 "BriefDescription": "Resource-related stall cycles",
692 "PublicDescription": "Cycles allocation is stalled due to resource related reason.",
697 "BriefDescription": "Cycles stalled due to re-order buffer full.",
705 "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
713 …"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining for…
717 …"PublicDescription": "This event counts cycles during which no instructions were allocated because…
731 "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
735 …cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buf…
751 "BriefDescription": "Cycles per thread when uops are executed in port 0.",
759 "BriefDescription": "Cycles per thread when uops are executed in port 1.",
767 "BriefDescription": "Cycles per thread when uops are executed in port 2.",
775 "BriefDescription": "Cycles per thread when uops are executed in port 3.",
783 "BriefDescription": "Cycles per thread when uops are executed in port 4.",
791 "BriefDescription": "Cycles per thread when uops are executed in port 5.",
799 "BriefDescription": "Cycles per thread when uops are executed in port 6.",
807 "BriefDescription": "Cycles per thread when uops are executed in port 7.",
825 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
835 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
845 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
855 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
865 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
875 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
881 …"PublicDescription": "This events counts the cycles where at least one uop was executed. It is cou…
886 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
892 …"PublicDescription": "This events counts the cycles where at least two uop were executed. It is co…
897 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
903 …"PublicDescription": "This events counts the cycles where at least three uop were executed. It is …
908 "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
918 …"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread…
929 "BriefDescription": "Cycles per thread when uops are executed in port 0",
933 "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.",
939 "BriefDescription": "Cycles per core when uops are executed in port 0.",
947 "BriefDescription": "Cycles per thread when uops are executed in port 1",
951 "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.",
957 "BriefDescription": "Cycles per core when uops are executed in port 1.",
965 "BriefDescription": "Cycles per thread when uops are executed in port 2",
969 "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.",
975 "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
983 "BriefDescription": "Cycles per thread when uops are executed in port 3",
987 "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.",
993 "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
1001 "BriefDescription": "Cycles per thread when uops are executed in port 4",
1005 "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.",
1011 "BriefDescription": "Cycles per core when uops are executed in port 4.",
1019 "BriefDescription": "Cycles per thread when uops are executed in port 5",
1023 "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.",
1029 "BriefDescription": "Cycles per core when uops are executed in port 5.",
1037 "BriefDescription": "Cycles per thread when uops are executed in port 6",
1041 "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.",
1047 "BriefDescription": "Cycles per core when uops are executed in port 6.",
1055 "BriefDescription": "Cycles per thread when uops are executed in port 7",
1059 "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.",
1065 "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
1083 …"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservatio…
1120 …"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservatio…
1135 …the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles.",
1141 "BriefDescription": "Cycles without actually retired uops.",
1161 "BriefDescription": "Cycles without actually retired uops.",
1171 "BriefDescription": "Cycles with less than 10 actually retired uops.",