Lines Matching +full:per +full:- +full:processor
3 "BriefDescription": "C2 residency percent per package",
4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
10 "BriefDescription": "C3 residency percent per core",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
17 "BriefDescription": "C3 residency percent per package",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
24 "BriefDescription": "C6 residency percent per core",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
31 "BriefDescription": "C6 residency percent per package",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
38 "BriefDescription": "C7 residency percent per core",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
45 "BriefDescription": "C7 residency percent per package",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
52 "BriefDescription": "Uncore frequency per die [GHZ]",
58 …"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instru…
230 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
237 … "MetricExpr": "(UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS) / UOPS_ISSUED.ANY",
255 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
280 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
298 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
304 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
309 …processor core where the out-of-order scheduler dispatches ready uops into their respective execut…
314 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
319 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
330 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
339 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
345 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
349 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
359 …sted accesses occur when data written by one Logical Processor are read by another Logical Process…
363 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
365 "MetricExpr": "tma_backend_bound - tma_memory_bound",
370 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
374 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
380 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
395 …"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UO…
404 …"MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks…
417 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
426 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
430 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
435 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
444 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
459 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
474 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
478 …"BriefDescription": "This category represents fraction of slots where the processor's Frontend und…
484 …processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor c…
488 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
494 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
506 …"BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower…
513 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
520 …"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
526 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
532 …cription": "Instruction-Level-Parallelism (average number of uops executed when there is execution…
546 …"BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower nu…
552 "BriefDescription": "Branch instructions per taken branch.",
565 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
572 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
579 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
586 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
593 "BriefDescription": "Instructions per taken branch",
598 …"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_…
601 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
607 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
613 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
619 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
625 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
631 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
637 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
643 "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
649 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
655 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
679 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
686 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
691 …cription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least…
732 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
739 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
763 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
767 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
790 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
796 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
802 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
808 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
814 "BriefDescription": "Uops Per Instruction",
821 "BriefDescription": "Uops per taken branch",
838 …"MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVI…
842 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
847 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_t…
884 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
885 "MetricExpr": "tma_retiring - tma_heavy_operations",
890 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
896 …HED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT…
925 "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
930 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
934 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
939 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
943 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
944 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
948 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
954 …- (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,…
959 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
973 …"MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_cl…
977 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
986 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
1008 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
1013 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
1017 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
1022 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
1026 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
1031 …sents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: U…
1053 …ents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
1058 …action of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with…
1062 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1064 …- (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,…
1068 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1072 … fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL…
1073 …SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYC…
1077 …ted no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherw…
1081 …on of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Proce…
1082 …_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_E…
1086 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
1090 …ts fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Proce…
1091 …_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_E…
1095 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
1099 …ion of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Proce…
1113 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
1122 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
1132 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
1136 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1142 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1151 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
1155 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1160 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1164 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1169 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
1178 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1184 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STO…
1188 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…