Lines Matching +full:per +full:- +full:stream

7         "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
12         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
36 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
53         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
63         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
93 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
102 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
153 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop…
158 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
167 …tion": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while…
177 …"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Inst…
195 …"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pip…
209 …"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the…
214 …"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend…
219 …-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. Th…
224 …"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocatio…
230 …-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the …
246 …"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocatio…