Lines Matching +full:per +full:- +full:processor
3 "BriefDescription": "C2 residency percent per package",
4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
10 "BriefDescription": "C3 residency percent per core",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
17 "BriefDescription": "C3 residency percent per package",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
24 "BriefDescription": "C6 residency percent per core",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
31 "BriefDescription": "C6 residency percent per package",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
38 "BriefDescription": "C7 residency percent per core",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
45 "BriefDescription": "C7 residency percent per package",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
52 "BriefDescription": "Uncore frequency per die [GHZ]",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
96 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
102 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
107 …processor core where the out-of-order scheduler dispatches ready uops into their respective execut…
112 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
117 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
128 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
137 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
143 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
147 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
157 …sted accesses occur when data written by one Logical Processor are read by another Logical Process…
161 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
163 "MetricExpr": "tma_backend_bound - tma_memory_bound",
168 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
172 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
178 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
193 …"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UO…
202 …"MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks…
215 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
224 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
228 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
233 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
242 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
257 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
272 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
276 …"BriefDescription": "This category represents fraction of slots where the processor's Frontend und…
282 …processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor c…
286 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
292 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
304 …"BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower…
311 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
318 …"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
324 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
330 …cription": "Instruction-Level-Parallelism (average number of uops executed when there is execution…
344 …"BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower nu…
350 "BriefDescription": "Branch instructions per taken branch.",
363 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
370 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
377 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
384 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
391 "BriefDescription": "Instructions per taken branch",
396 …"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_…
399 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
405 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
411 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
417 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
423 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
429 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
435 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
441 "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
447 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
453 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
477 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
484 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
489 …cription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least…
530 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
537 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
551 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
568 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
574 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
580 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
586 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
592 "BriefDescription": "Uops Per Instruction",
599 "BriefDescription": "Uops per taken branch",
616 …"MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVI…
620 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
625 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_t…
662 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
663 "MetricExpr": "tma_retiring - tma_heavy_operations",
668 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
674 …HED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT…
694 "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
699 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
703 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
708 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
712 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
713 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
717 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
723 …- (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,…
728 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
742 …"MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_cl…
746 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
755 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
777 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
782 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
786 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
791 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
795 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
800 …sents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: U…
822 …ents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
827 …action of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with…
831 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
833 …- (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,…
837 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
841 … fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL…
842 …SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYC…
846 …ted no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherw…
850 …on of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Proce…
851 …_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_E…
855 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
859 …ts fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Proce…
860 …_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_E…
864 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
868 …ion of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Proce…
882 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
886 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
892 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
901 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
905 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
910 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
914 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
919 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
928 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
934 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STO…
938 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…