x86/graniterapids/pipeline.json

8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
157         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
167 …"BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise …
195 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
200 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
257 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
271 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
275 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
280 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
284 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
338 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
511         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
515 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
520         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
525 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
548         "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
552 …ons Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Cou…
562 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
618 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
639         "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
643 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
648         "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
652 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
720 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
730 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
740 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
749 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
765         "BriefDescription": "Self-modifying code (SMC) detected.",
769 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
800 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
804 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
813 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
822 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
835 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
838 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
843 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
847 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
852         "BriefDescription": "Number of non dec-by-all uops decoded by decoder",
856 …  "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.",
933 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
938 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
943 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
948 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
953 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
958 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
963 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
968 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
973         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
978         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
983         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
988         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
993         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
998         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1003         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1008         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1024         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1073 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1088 …orrelates with higher performance  for example, as measured by the instructions-per-cycle metric.",
1092 …he instructions-per-cycle metric. Software can use this event as the numerator for the Retiring me…