Lines Matching +full:1 +full:- +full:6
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
14 "Counter": "0,1,2,3,4,5,6,7",
15 "CounterMask": "1",
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
41 "Counter": "0,1,2,3,4,5,6,7",
44 "PEBS": "1",
51 "Counter": "0,1,2,3,4,5,6,7",
54 "PEBS": "1",
61 "Counter": "0,1,2,3,4,5,6,7",
64 "PEBS": "1",
71 "Counter": "0,1,2,3,4,5,6,7",
74 "PEBS": "1",
81 "Counter": "0,1,2,3,4,5,6,7",
84 "PEBS": "1",
91 "Counter": "0,1,2,3,4,5,6,7",
94 "PEBS": "1",
101 "Counter": "0,1,2,3,4,5,6,7",
104 "PEBS": "1",
111 "Counter": "0,1,2,3,4,5,6,7",
114 "PEBS": "1",
121 "Counter": "0,1,2,3,4,5,6,7",
124 "PEBS": "1",
130 "Counter": "0,1,2,3,4,5,6,7",
133 "PEBS": "1",
139 "Counter": "0,1,2,3,4,5,6,7",
142 "PEBS": "1",
149 "Counter": "0,1,2,3,4,5,6,7",
152 "PEBS": "1",
157 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
158 "Counter": "0,1,2,3,4,5,6,7",
161 "PEBS": "1",
167 …"BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise …
168 "Counter": "0,1,2,3,4,5,6,7",
171 "PEBS": "1",
177 "Counter": "0,1,2,3,4,5,6,7",
180 "PEBS": "1",
187 "Counter": "0,1,2,3,4,5,6,7",
190 "PEBS": "1",
195 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
196 "Counter": "0,1,2,3,4,5,6,7",
199 "PEBS": "1",
200 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
206 "Counter": "0,1,2,3,4,5,6,7",
209 "PEBS": "1",
216 "Counter": "0,1,2,3,4,5,6,7",
219 "PEBS": "1",
225 "Counter": "0,1,2,3,4,5,6,7",
228 "PEBS": "1",
234 "Counter": "0,1,2,3,4,5,6,7",
237 "PEBS": "1",
244 "Counter": "0,1,2,3,4,5,6,7",
247 "PEBS": "1",
253 "Counter": "0,1,2,3,4,5,6,7",
256 "PEBS": "1",
257 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
263 "Counter": "0,1,2,3,4,5,6,7",
266 "PEBS": "1",
271 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
272 "Counter": "0,1,2,3,4,5,6,7",
275 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
280 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
281 "Counter": "0,1,2,3,4,5,6,7",
284 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
289 …"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 A…
290 "Counter": "0,1,2,3,4,5,6,7",
293 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optim…
299 "Counter": "0,1,2,3,4,5,6,7",
308 "Counter": "0,1,2,3,4,5,6,7",
317 "Counter": "0,1,2,3,4,5,6,7",
325 "Counter": "0,1,2,3,4,5,6,7",
326 "CounterMask": "1",
327 "EdgeDetect": "1",
335 "Counter": "0,1,2,3,4,5,6,7",
338 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
346 …1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counte…
352 "Counter": "0,1,2,3,4,5,6,7",
355 …1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counte…
361 "Counter": "Fixed counter 1",
369 "Counter": "0,1,2,3,4,5,6,7",
377 "Counter": "0,1,2,3",
386 "Counter": "0,1,2,3",
387 "CounterMask": "1",
395 "Counter": "0,1,2,3,4,5,6,7",
404 "Counter": "0,1,2,3",
413 "Counter": "0,1,2,3",
422 "Counter": "0,1,2,3,4,5,6,7",
430 …"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was no…
431 "Counter": "0,1,2,3,4,5,6,7",
433 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
434 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
440 "Counter": "0,1,2,3,4,5,6,7",
448 "Counter": "0,1,2,3,4,5,6,7",
457 "Counter": "0,1,2,3,4,5,6,7",
466 "Counter": "0,1,2,3,4,5,6,7",
475 "Counter": "0,1,2,3,4,5,6,7",
484 "Counter": "0,1,2,3,4,5,6,7",
494 "Counter": "0,1,2,3,4,5,6,7",
503 "Counter": "0,1,2,3",
511 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
514 "PEBS": "1",
515 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
520 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
521 "Counter": "0,1,2,3,4,5,6,7",
524 "PEBS": "1",
525 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
530 "Counter": "0,1,2,3,4,5,6,7",
533 "PEBS": "1",
539 "Counter": "0,1,2,3,4,5,6,7",
542 "PEBS": "1",
543 "PublicDescription": "Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions",
548 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
551 "PEBS": "1",
558 "Counter": "0,1,2,3,4,5,6,7",
561 "PEBS": "1",
562 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
568 "Counter": "0,1,2,3,4,5,6,7",
569 "CounterMask": "1",
570 "EdgeDetect": "1",
579 "Counter": "0,1,2,3,4,5,6,7",
588 "Counter": "0,1,2,3,4,5,6,7",
596 "Counter": "0,1,2,3,4,5,6,7",
605 "Counter": "0,1,2,3,4,5,6,7",
615 "Counter": "0,1,2,3,4,5,6,7",
618 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
624 "Counter": "0,1,2,3,4,5,6,7",
632 "Counter": "0,1,2,3,4,5,6,7",
639 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
640 "Counter": "0,1,2,3,4,5,6,7",
643 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
648 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
649 "Counter": "0,1,2,3,4,5,6,7",
652 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
658 "Counter": "0,1,2,3,4,5,6,7",
666 "Counter": "0,1,2,3,4,5,6,7",
674 "Counter": "0,1,2,3,4,5,6,7",
682 "Counter": "0,1,2,3,4,5,6,7",
690 "Counter": "0,1,2,3",
699 "Counter": "0,1,2,3",
708 "Counter": "0,1,2,3",
717 "Counter": "0,1,2,3",
720 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
726 "Counter": "0,1,2,3,4,5,6,7",
727 "CounterMask": "1",
730 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
736 "Counter": "0,1,2,3,4,5,6,7",
737 "CounterMask": "6",
740 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
746 "Counter": "0,1,2,3,4,5,6,7",
749 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
755 "Counter": "0,1,2,3,4,5,6,7",
756 "CounterMask": "1",
757 "EdgeDetect": "1",
765 "BriefDescription": "Self-modifying code (SMC) detected.",
766 "Counter": "0,1,2,3,4,5,6,7",
769 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
775 "Counter": "0,1,2,3,4,5,6,7",
784 "Counter": "0,1,2,3,4,5,6,7",
793 "Counter": "0,1,2,3,4,5,6,7",
800 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
801 "Counter": "0,1,2,3,4,5,6,7",
804 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
813 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
822 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
828 "Counter": "0,1,2,3,4,5,6,7",
835 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
838 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
843 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
844 "Counter": "0,1,2,3,4,5,6,7",
847 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
852 "BriefDescription": "Number of non dec-by-all uops decoded by decoder",
853 "Counter": "0,1,2,3",
856 … "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.",
862 "Counter": "0,1,2,3,4,5,6,7",
870 "BriefDescription": "Uops executed on port 1",
871 "Counter": "0,1,2,3,4,5,6,7",
874 "PublicDescription": "Number of uops dispatch to execution port 1.",
880 "Counter": "0,1,2,3,4,5,6,7",
889 "Counter": "0,1,2,3,4,5,6,7",
898 "Counter": "0,1,2,3,4,5,6,7",
906 "BriefDescription": "Uops executed on port 6",
907 "Counter": "0,1,2,3,4,5,6,7",
910 "PublicDescription": "Number of uops dispatch to execution port 6.",
916 "Counter": "0,1,2,3,4,5,6,7",
925 "Counter": "0,1,2,3,4,5,6,7",
933 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
934 "Counter": "0,1,2,3,4,5,6,7",
935 "CounterMask": "1",
938 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
943 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
944 "Counter": "0,1,2,3,4,5,6,7",
948 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
953 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
954 "Counter": "0,1,2,3,4,5,6,7",
958 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
963 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
964 "Counter": "0,1,2,3,4,5,6,7",
968 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
973 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
974 "Counter": "0,1,2,3,4,5,6,7",
975 "CounterMask": "1",
978 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
983 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
984 "Counter": "0,1,2,3,4,5,6,7",
988 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
993 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
994 "Counter": "0,1,2,3,4,5,6,7",
998 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1003 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1004 "Counter": "0,1,2,3,4,5,6,7",
1008 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1014 "Counter": "0,1,2,3,4,5,6,7",
1015 "CounterMask": "1",
1018 "Invert": "1",
1024 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1025 "Counter": "0,1,2,3,4,5,6,7",
1033 "Counter": "0,1,2,3,4,5,6,7",
1042 "Counter": "0,1,2,3,4,5,6,7",
1051 "Counter": "0,1,2,3,4,5,6,7",
1052 "CounterMask": "1",
1060 "Counter": "0,1,2,3,4,5,6,7",
1061 "CounterMask": "1",
1070 "Counter": "0,1,2,3,4,5,6,7",
1073 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1079 "Counter": "0,1,2,3,4,5,6,7",
1088 …orrelates with higher performance for example, as measured by the instructions-per-cycle metric.",
1089 "Counter": "0,1,2,3,4,5,6,7",
1092 …he instructions-per-cycle metric. Software can use this event as the numerator for the Retiring me…
1098 "Counter": "0,1,2,3,4,5,6,7",
1099 "CounterMask": "1",
1102 "Invert": "1",