x86/graniterapids/frontend.json

7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
29         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
57 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
69 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
110         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
117 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n…
122 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
129 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
134 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not …
141 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this …
146         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
153 …ter an interval where the front-end delivered no uops for a period of at least 2 cycles which was …
158 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
165 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
170 …ter an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was …
177 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
182 …d after an interval where the front-end delivered no uops for a period of 32 cycles which was not …
189 …ons that are delivered to the back-end after a front-end stall of at least 32 cycles. During this …
194 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
201 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
206 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
213 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
218 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
225 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
230 …d after an interval where the front-end delivered no uops for a period of 8 cycles which was not i…
237 …ions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this …
242         "BriefDescription": "I-Cache miss too close to Code Prefetch Instruction",
249 …tion": "Number of Instruction Cache demand miss in shadow of an on-going i-fetch cache-line trigge…
416 …hen no operation was delivered to the back-end pipeline due to instruction fetch limitations when …
420 …-end pipeline due to instruction fetch limitations when the back-end could have accepted more oper…
430 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
435 …n": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not sta…
441 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
450 … to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
460 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
465 …n": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not sta…
471 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…