x86/graniterapids/frontend.json

7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
29         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
57 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
69 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
110         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
117 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
122 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
129 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
134 … after an interval where the front-end delivered no uops for a period of 16 cycles which was not i…
141 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
146         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
153 …er an interval where the front-end delivered no uops for a period of at least 2 cycles which was n…
158 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
165 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
170 …er an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was n…
177 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
182 … after an interval where the front-end delivered no uops for a period of 32 cycles which was not i…
189 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
194 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
201 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
206 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
213 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
218 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
225 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
230 … after an interval where the front-end delivered no uops for a period of 8 cycles which was not in…
237 …tions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this…
242         "BriefDescription": "I-Cache miss too close to Code Prefetch Instruction",
249 …tion": "Number of Instruction Cache demand miss in shadow of an on-going i-fetch cache-line trigge…
391 …code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream…
407 …"BriefDescription": "Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruc…
411 …"PublicDescription": "Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) an…
416 … when no operation was delivered to the back-end pipeline due to instruction fetch limitations whe…
420 …-end pipeline due to instruction fetch limitations when the back-end could have accepted more oper…
430 …ered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-…
435 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
441 …ered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-…
450 …d to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-…
460 …ered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-…
465 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
471 …ered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-…