Lines Matching +full:6 +full:a

7 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
39         "Counter": "0,1,2,3,4,5,6,7",
51         "Counter": "0,1,2,3,4,5,6,7",
62         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
63         "Counter": "0,1,2,3,4,5,6,7",
69 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
75         "Counter": "0,1,2,3,4,5,6,7",
87         "Counter": "0,1,2,3,4,5,6,7",
99         "Counter": "0,1,2,3,4,5,6,7",
111         "Counter": "0,1,2,3,4,5,6,7",
117 …rval where the front-end delivered no uops for a period of at least 1 cycle which was not interrup…
122 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
123         "Counter": "0,1,2,3,4,5,6,7",
129 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
134 …nterval where the front-end delivered no uops for a period of 16 cycles which was not interrupted …
135         "Counter": "0,1,2,3,4,5,6,7",
141 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
147         "Counter": "0,1,2,3,4,5,6,7",
153 …val where the front-end delivered no uops for a period of at least 2 cycles which was not interrup…
158 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
159         "Counter": "0,1,2,3,4,5,6,7",
165 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
170 …where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted …
171         "Counter": "0,1,2,3,4,5,6,7",
177 … the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-sl…
182 …nterval where the front-end delivered no uops for a period of 32 cycles which was not interrupted …
183         "Counter": "0,1,2,3,4,5,6,7",
189 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
194 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
195         "Counter": "0,1,2,3,4,5,6,7",
201 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
206 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
207         "Counter": "0,1,2,3,4,5,6,7",
213 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
218 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
219         "Counter": "0,1,2,3,4,5,6,7",
225 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
230 …interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted …
231         "Counter": "0,1,2,3,4,5,6,7",
237 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
243         "Counter": "0,1,2,3,4,5,6,7",
255         "Counter": "0,1,2,3,4,5,6,7",
267         "Counter": "0,1,2,3,4,5,6,7",
278         "Counter": "0,1,2,3,4,5,6,7",
290         "Counter": "0,1,2,3,4,5,6,7",
300 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
304 …tion": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The …
319 …  "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
323 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
340         "CounterMask": "6",
369         "CounterMask": "6",
416 …"BriefDescription": "This event counts a subset of the Topdown Slots event that when no operation …
417         "Counter": "0,1,2,3,4,5,6,7",
420 …"PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation…
426         "Counter": "0,1,2,3,4,5,6,7",
427         "CounterMask": "6",
430 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
436         "Counter": "0,1,2,3,4,5,6,7",
441 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
447         "Counter": "0,1,2,3,4,5,6,7",
450 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
456         "Counter": "0,1,2,3,4,5,6,7",
457         "CounterMask": "6",
460 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
466         "Counter": "0,1,2,3,4,5,6,7",
471 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…