x86/grandridge/virtual-memory.json

3 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de…
11         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.",
19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
23 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc…
28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
32 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc…
46 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor…
54 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa…
62 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or…
66 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl…
71 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K pa…
75 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl…
97 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to an i…
105 …"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to …
109 …"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose a…
114 …"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to …
118 …"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose a…
123 …"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to …
127 …"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose a…
141 …hat the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",