Lines Matching +full:1 +full:- +full:based

4         "Counter": "0,1,2,3",
13         "Counter": "0,1,2,3",
22         "Counter": "0,1,2,3",
31         "Counter": "0,1,2,3",
39 …nces per ICache line. This event counts differently than Intel processors based on Silvermont micr…
40         "Counter": "0,1,2,3",
43 … is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont micr…
48 … in the ICache (hit). This event counts differently than Intel processors based on Silvermont micr…
49         "Counter": "0,1,2,3",
52 …ine is in the ICache. This event counts differently than Intel processors based on Silvermont micr…
57 …in the ICache (miss). This event counts differently than Intel processors based on Silvermont micr…
58         "Counter": "0,1,2,3",
61 …is not in the ICache. This event counts differently than Intel processors based on Silvermont micr…
67         "Counter": "0,1,2,3",
70 … read from the MSROM.  The most common case that this counts is when a micro-coded instruction is …