x86/goldmontplus/cache.json

217 …"BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the…
223 …"PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from th…
272 …ounts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore …
278 …ounts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore …
327 …d for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore …
333 …d for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore …
382 …"BriefDescription": "Counts requests to the uncore subsystem have any transaction responses from t…
388 …ription": "Counts requests to the uncore subsystem have any transaction responses from the uncore …
437 …s for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore …
443 …s for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore …
492 …"BriefDescription": "Counts bus lock and split lock requests have any transaction responses from t…
498 …ription": "Counts bus lock and split lock requests have any transaction responses from the uncore …
547 …ck transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore …
553 …ck transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore …
602 … prefetch requests that miss the instruction cache have any transaction responses from the uncore …
608 … prefetch requests that miss the instruction cache have any transaction responses from the uncore …
657 …ts demand cacheable data reads of full cache lines have any transaction responses from the uncore …
663 …ts demand cacheable data reads of full cache lines have any transaction responses from the uncore …
712 …uests generated by a write to full data cache line have any transaction responses from the uncore …
718 …uests generated by a write to full data cache line have any transaction responses from the uncore …
767 …ory region and full cache-line non-temporal writes have any transaction responses from the uncore …
773 …ory region and full cache-line non-temporal writes have any transaction responses from the uncore …
822 …ads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore …
828 …ads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore …
877 …ne reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore …
883 …ne reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore …
932 …wnership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore …
938 …wnership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore …
987 … uncacheable write combining (USWC) memory region  have any transaction responses from the uncore …
993 … uncacheable write combining (USWC) memory region  have any transaction responses from the uncore …
1042 …e lines requests by software prefetch instructions have any transaction responses from the uncore …
1048 …e lines requests by software prefetch instructions have any transaction responses from the uncore …