x86/goldmontplus/cache.json

20         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
33 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
72 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the …
176         "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
187         "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
198         "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
239 …ads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
245 …ads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
250 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
256 …d & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Require…
261 …"BriefDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time o…
267 …"PublicDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time …
294 …by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data for…
300 …by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data for…
305 … L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.",
311 …2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.  Require…
316 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, f…
322 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, …
349 …sts (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
355 …sts (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
360 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
366 …d & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Require…
371 …ad, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the tim…
377 …ad, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the tim…
404 …to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data for…
410 …to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data for…
415 … the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.",
421 …ore subsystem true miss for the L2 cache with a snoop miss in the other processor module.  Require…
426 …"BriefDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time…
432 …"PublicDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the tim…
459 …sts (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
465 …sts (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
470 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
476 …d & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Require…
481 …Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the tim…
487 …Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the tim…
514 …and split lock requests miss the L2 cache with a snoop hit in the other processor module, data for…
520 …and split lock requests miss the L2 cache with a snoop hit in the other processor module, data for…
525 …d split lock requests true miss for the L2 cache with a snoop miss in the other processor module.",
531 …lock requests true miss for the L2 cache with a snoop miss in the other processor module.  Require…
536 …"BriefDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time…
542 …"PublicDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the tim…
569 …1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data for…
575 …1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data for…
580 …or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.",
586 …che evictions true miss for the L2 cache with a snoop miss in the other processor module.  Require…
591 … of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the tim…
597 … of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the tim…
602 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
608 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t…
613 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
619 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t…
624 …tion cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with…
630 …tion cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with…
635 …cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache …
641 …cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache …
646 …ounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache ou…
652 …ounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache ou…
679 …ads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data for…
685 …ads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data for…
690 …s of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.",
696 …l cache lines true miss for the L2 cache with a snoop miss in the other processor module.  Require…
701 …ion": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the tim…
707 …ion": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the tim…
734 …to full data cache line miss the L2 cache with a snoop hit in the other processor module, data for…
740 …to full data cache line miss the L2 cache with a snoop hit in the other processor module, data for…
745 … full data cache line true miss for the L2 cache with a snoop miss in the other processor module.",
751 …ta cache line true miss for the L2 cache with a snoop miss in the other processor module.  Require…
756 …p (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the tim…
762 …p (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the tim…
767 …ites to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes h…
773 …ites to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes h…
778 …ites to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes h…
784 …ites to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes h…
789 …(USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in…
795 …(USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in…
800 …) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop mi…
806 …) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop mi…
811 …ble write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per …
817 …ble write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per …
844 …1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data for…
850 …1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data for…
855 …data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
861 …he prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Require…
866 …che line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the tim…
872 …che line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the tim…
899 …are L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data for…
905 …are L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data for…
910 …e L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
916 …he prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Require…
921 …ata cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the tim…
927 …ata cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the tim…
954 …erated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data for…
960 …erated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data for…
965 …ated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
971 …L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Require…
976 …reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the tim…
982 …reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the tim…
1009 …g (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data for…
1015 …g (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data for…
1020 …(USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.",
1026 …emory region  true miss for the L2 cache with a snoop miss in the other processor module.  Require…
1031 …a writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the tim…
1037 …a writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the tim…
1064 …e prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data for…
1070 …e prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data for…
1075 …prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.",
1081 … instructions true miss for the L2 cache with a snoop miss in the other processor module.  Require…
1086 …s data cache lines requests by software prefetch instructions outstanding, per cycle, from the tim…
1092 …s data cache lines requests by software prefetch instructions outstanding, per cycle, from the tim…