x86/goldmont/pipeline.json

116 …branch instructions retired, where the target address taken was not what the processor predicted.",
126 … supposed to be taken and when it was not supposed to be taken (but the processor predicted the op…
136 …t call or near indirect jmp, where the target address taken was not what the processor predicted.",
146 …branch instructions retired, where the return address taken was not what the processor predicted.",
156 …Met) branch instructions retired that were supposed to be taken but the processor predicted that i…
228         "BriefDescription": "Unfilled issue slots per cycle",
232 … slots per core cycle that were not consumed by the backend due to either a full resource  in the …
236         "BriefDescription": "Unfilled issue slots per cycle to recover",
240 …slots per core cycle that were not consumed by the backend because allocation is stalled waiting f…
245 …    "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
249 …e slots per core cycle that were not consumed because of a full resource in the backend.  Includin…
321         "BriefDescription": "Self-Modifying Code detected",
325 … that the processor detects that a program is writing to a code section and has to perform a machi…
330         "BriefDescription": "Uops issued to the back end per cycle",
334 …ed includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, tho…
338         "BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
342 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
370 …ued by the micro-sequencer (MS).  Counts both the uops from a micro-coded instruction, and the uop…