x86/emeraldrapids/pipeline.json

18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
169         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
189 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
194 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
224 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
229 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
233 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
238 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
242 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
296 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
469         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
473 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
478         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
483 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
506         "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
510 …ons Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Cou…
520 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
576 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
597         "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
601 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
606         "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
610 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
678 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
688 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
698 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
707 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
723         "BriefDescription": "Self-modifying code (SMC) detected.",
727 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
754 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
767 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
771 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
780 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
789 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
802 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
805 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
810 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
814 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
899 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
904 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
909 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
914 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
919 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
924 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
929 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
934 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
939         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
944         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
949         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
954         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
959         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
964         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
969         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
974         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1001         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1050 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …