x86/cascadelakex/floating-point.json

3 …riefDescription": "Counts once for most SIMD 128-bit packed computational double precision floatin…
4         "Counter": "0,1,2,3",
7 …-bit packed computational double precision floating-point instructions retired; some instructions …
12 …riefDescription": "Counts once for most SIMD 128-bit packed computational single precision floatin…
13         "Counter": "0,1,2,3",
16 …-bit packed computational single precision floating-point instructions retired; some instructions …
21 …riefDescription": "Counts once for most SIMD 256-bit packed double computational precision floatin…
22         "Counter": "0,1,2,3",
25 …-bit packed double computational precision floating-point instructions retired; some instructions …
30 …riefDescription": "Counts once for most SIMD 256-bit packed single computational precision floatin…
31         "Counter": "0,1,2,3",
34 …-bit packed single computational precision floating-point instructions retired; some instructions …
39 …"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed doub…
40         "Counter": "0,1,2,3",
43 …-bit packed single precision and 256-bit packed double precision  floating-point instructions reti…
48 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
49         "Counter": "0,1,2,3",
52 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
57 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
58         "Counter": "0,1,2,3",
61 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
66 …"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit p…
67         "Counter": "0,1,2,3",
70 …-bit packed single precision and 512-bit packed double precision  floating-point instructions reti…
75 …"BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions re…
76         "Counter": "0,1,2,3",
79 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
84 …"Counts once for most SIMD scalar computational double precision floating-point instructions retir…
85         "Counter": "0,1,2,3",
88 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
93 …"Counts once for most SIMD scalar computational single precision floating-point instructions retir…
94         "Counter": "0,1,2,3",
97 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
103         "Counter": "0,1,2,3",
110 …   "BriefDescription": "Intel AVX-512 computational 512-bit packed BFloat16 instructions retired.",
111         "Counter": "0,1,2,3",
114 …licDescription": "Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floatin…
119 …   "BriefDescription": "Intel AVX-512 computational 128-bit packed BFloat16 instructions retired.",
120         "Counter": "0,1,2,3",
123 …licDescription": "Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floatin…
128 …   "BriefDescription": "Intel AVX-512 computational 256-bit packed BFloat16 instructions retired.",
129         "Counter": "0,1,2,3",
132 …licDescription": "Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floatin…
138         "Counter": "0,1,2,3",