x86/broadwellx/bdx-metrics.json

4         "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
5         "MetricGroup": "Power",
11         "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
12         "MetricGroup": "Power",
18         "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
19         "MetricGroup": "Power",
25         "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
26         "MetricGroup": "Power",
32         "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
33         "MetricGroup": "Power",
39         "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
40         "MetricGroup": "Power",
46         "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
47         "MetricGroup": "Power",
70         "BriefDescription": "Percentage of time spent in the active CPU power state C0",
164 …"BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read mis…
170 …"BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read mis…
176 …"BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read mis…
230 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
255         "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
280 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
298 …-cases for operations that cannot be handled natively by the execution pipeline. For example; when…
304         "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
309 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
314 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
319 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
330 …ram path; or stalls when the out-of-order part of the machine needs to recover its state from a sp…
339 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
345         "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
349 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
368 … true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_…
372 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
374         "MetricExpr": "tma_backend_bound - tma_memory_bound",
379 …-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in s…
383 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
389 …-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause in…
398 …than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDE…
404 …"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UO…
408 … loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOP…
413 …"MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks…
426 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
435 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
439 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
444 …-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and…
453 …ultiple Logical Processors contend on different data-elements mapped into the same cache line. Sam…
468         "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
483 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
487 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
492 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
496 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
501 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
505 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
510 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
514 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
519 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
523 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
528 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
538 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
542 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
548 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
567 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
580         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
592 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
596 …-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
599 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
629 …   "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST"
640 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
645 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
648 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
653 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
656 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
661 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
664 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
669 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
715         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
721         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
727         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
733 …      "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
745         "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
752         "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
787         "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
799         "BriefDescription": "Average Parallel L2 cache miss data reads",
805         "BriefDescription": "Average Latency for L2 cache miss demand Loads",
811         "BriefDescription": "Average Parallel L2 cache miss demand Loads",
817 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
824 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
829 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
839 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
845 …"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
851         "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]",
853         "MetricGroup": "Power;Summary",
857         "BriefDescription": "Average CPU Utilization (percentage)",
863         "BriefDescription": "Average number of utilized CPUs",
869         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
873 …"PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Relat…
880 …egate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
903         "BriefDescription": "Average number of parallel data read requests to external memory",
907 …"PublicDescription": "Average number of parallel data read requests to external memory. Accounts f…
910 …    "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)",
914 …tion": "Average latency of data read request to external memory (in nanoseconds). Accounts for dem…
918 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
929         "BriefDescription": "Average Frequency Utilization relative nominal frequency",
931         "MetricGroup": "Power",
935         "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]",
941 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
953         "BriefDescription": "The ratio of Executed- by Issued-Uops",
957 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
966 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
991 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
996 …"MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thr…
1000 …t stalls; while some non-completed demand load lives in the machine without having that demand loa…
1005 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_…
1009 ….e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOP…
1019 ….e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOP…
1029 …performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOP…
1042 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1043         "MetricExpr": "tma_retiring - tma_heavy_operations",
1048 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1054 …HED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT…
1058 …ion of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATC…
1067 …local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOP…
1077 … classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RET…
1083         "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
1088 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1092 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1097 …- DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic i…
1101 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1102 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1106 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1112 …CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS…
1117 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1126 …odes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS.…
1140 …"MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_cl…
1144 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
1153 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
1162 …atched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATC…
1171 …s Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATC…
1175 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
1180 …PU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with:…
1184 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
1189 …PU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with:…
1193 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
1198 …ore fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DIS…
1207 …spatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATC…
1216 …patched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATC…
1220 …ents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
1225 …f cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_D…
1229 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1231 …- (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2…
1235 …-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1240 …ED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYC…
1244 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
1249 …_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECU…
1253 …-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
1258 …_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECU…
1262 …cal Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options…
1280 …izations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. …
1289 …m remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. …
1299 …-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no r…
1303 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1309 …ion of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. S…
1318 …lit store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample wit…
1322 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1327 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1331 … CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1336 …-for-ownership request before the write. Even though store accesses do not typically stall out-of-…
1345 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1351 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STO…
1355 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
1368         "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
1372 …is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY…