x86/amdzen5/recommended.json

4     "BriefDescription": "Execution-time branch misprediction rate (non-speculative).",
11     "BriefDescription": "All data cache accesses per thousand instructions.",
18     "BriefDescription": "All L2 cache accesses per thousand instructions.",
25 …"BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch) per t…
32 …"BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch) per thousand…
39 …"BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher per thousand instructions…
46     "BriefDescription": "All L2 cache misses per thousand instructions.",
53 … "BriefDescription": "L2 cache misses from L1 instruction cache misses per thousand instructions.",
60     "BriefDescription": "L2 cache misses from L1 data cache misses per thousand instructions.",
67 …"BriefDescription": "L2 cache misses from L2 cache hardware prefetcher per thousand instructions.",
74     "BriefDescription": "All L2 cache hits per thousand instructions.",
81     "BriefDescription": "L2 cache hits from L1 instruction cache misses per thousand instructions.",
88     "BriefDescription": "L2 cache hits from L1 data cache misses per thousand instructions.",
95 …  "BriefDescription": "L2 cache hits from L2 cache hardware prefetcher per thousand instructions.",
102     "BriefDescription": "L3 cache accesses.",
135     "BriefDescription": "Op cache miss ratio for all fetches.",
141 …"BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will …
147 …"BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructi…
154     "BriefDescription": "L1 data cache fills from a different NUMA node per thousand instructions.",
161     "BriefDescription": "L1 data cache fills from within the same CCX per thousand instructions.",
168 …"BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node per thousand inst…
175     "BriefDescription": "All L1 data cache fills per thousand instructions.",
182     "BriefDescription": "L1 demand data cache fills from local L2 cache per thousand instructions.",
189 …"BriefDescription": "L1 demand data cache fills from within the same CCX per thousand instructions…
196 …"BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node per t…
203 …"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node per thousa…
210 …"BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node pe…
217 …"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node per tho…
259     "BriefDescription": "Macro-ops dispatched.",
270     "BriefDescription": "Macro-ops retired.",
275     "BriefDescription": "Memory controller data bus utilization.",
283     "BriefDescription": "Memory controller CAS command rate.",
291     "BriefDescription": "Ratio of memory controller CAS commands for reads.",
299     "BriefDescription": "Ratio of memory controller CAS commands for writes.",
331     "BriefDescription": "Memory controller ACTIVATE command rate.",
339     "BriefDescription": "Memory controller PRECHARGE command rate.",