x86/amdzen5/recommended.json

25 …"BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch) per t…
32 …"BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch) per thousand…
53 … "BriefDescription": "L2 cache misses from L1 instruction cache misses per thousand instructions.",
60     "BriefDescription": "L2 cache misses from L1 data cache misses per thousand instructions.",
81     "BriefDescription": "L2 cache hits from L1 instruction cache misses per thousand instructions.",
88     "BriefDescription": "L2 cache hits from L1 data cache misses per thousand instructions.",
147 …"BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructi…
154     "BriefDescription": "L1 data cache fills from a different NUMA node per thousand instructions.",
161     "BriefDescription": "L1 data cache fills from within the same CCX per thousand instructions.",
168 …"BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node per thousand inst…
175     "BriefDescription": "All L1 data cache fills per thousand instructions.",
182     "BriefDescription": "L1 demand data cache fills from local L2 cache per thousand instructions.",
189 …"BriefDescription": "L1 demand data cache fills from within the same CCX per thousand instructions…
196 …"BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node per t…
203 …"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node per thousa…
210 …"BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node pe…
217 …"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node per tho…
224     "BriefDescription": "L1 instruction TLB misses per thousand instructions.",
238     "BriefDescription": "L1 data TLB misses per thousand instructions.",