x86/amdzen4/recommended.json

4     "BriefDescription": "Execution-time branch misprediction ratio (non-speculative).",
12     "BriefDescription": "All data cache accesses.",
17     "BriefDescription": "All L2 cache accesses.",
23     "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
29     "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
35     "BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher.",
41     "BriefDescription": "All L2 cache misses.",
47     "BriefDescription": "L2 cache misses from L1 instruction cache misses.",
53     "BriefDescription": "L2 cache misses from L1 data cache misses.",
59     "BriefDescription": "L2 cache misses from L2 cache hardware prefetcher.",
65     "BriefDescription": "All L2 cache hits.",
71     "BriefDescription": "L2 cache hits from L1 instruction cache misses.",
77     "BriefDescription": "L2 cache hits from L1 data cache misses.",
83     "BriefDescription": "L2 cache hits from L2 cache hardware prefetcher.",
89     "BriefDescription": "L3 cache accesses.",
108     "BriefDescription": "Op cache miss ratio for all fetches.",
114 …"BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will …
120     "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.",
126     "BriefDescription": "L1 data cache fills from a different NUMA node.",
132     "BriefDescription": "L1 data cache fills from within the same CCX.",
138     "BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node.",
144     "BriefDescription": "All L1 data cache fills.",
150     "BriefDescription": "L1 demand data cache fills from local L2 cache.",
156     "BriefDescription": "L1 demand data cache fills from within the same CCX.",
162     "BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node.",
168     "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node.",
174 … "BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node.",
180     "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node.",
216     "BriefDescription": "Macro-ops dispatched.",
227     "BriefDescription": "Macro-ops retired.",
236     "ScaleUnit": "6.103515625e-5MiB"
244     "ScaleUnit": "6.103515625e-5MiB"
252     "ScaleUnit": "6.103515625e-5MiB"
260     "ScaleUnit": "6.103515625e-5MiB"
268     "ScaleUnit": "6.103515625e-5MiB"
276     "ScaleUnit": "6.103515625e-5MiB"
284     "ScaleUnit": "6.103515625e-5MiB"
292     "ScaleUnit": "6.103515625e-5MiB"
300     "ScaleUnit": "3.0517578125e-5MiB"
308     "ScaleUnit": "6.103515625e-5MiB"
316     "ScaleUnit": "3.0517578125e-5MiB"
324     "ScaleUnit": "6.103515625e-5MiB"
332     "ScaleUnit": "6.103515625e-5MiB"
336     "BriefDescription": "Memory controller data bus utilization.",
344     "BriefDescription": "Memory controller CAS command rate.",
351     "BriefDescription": "Ratio of memory controller CAS commands for reads.",
359     "BriefDescription": "Ratio of memory controller CAS commands for writes.",
391     "BriefDescription": "Ratio of memory controller CAS commands for reads.",
399     "BriefDescription": "Memory controller CAS command rate.",
406     "BriefDescription": "Memory controller ACTIVATE command rate.",
413     "BriefDescription": "Memory controller PRECHARGE command rate.",