x86/amdzen4/cache.json

5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all…
11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har…
17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all…
23     "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the…
41     "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d…
53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa…
59     "BriefDescription": "Demand data cache fills from extension memory.",
65     "BriefDescription": "Demand data cache fills from all types of data sources.",
71     "BriefDescription": "Any data cache fills from local L2 cache.",
77     "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
83 …"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in…
89 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the sa…
95     "BriefDescription": "Any data cache fills from either DRAM or MMIO in the same NUMA node.",
101 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in a diff…
107 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the sa…
113 …"BriefDescription": "Any data cache fills from either DRAM or MMIO in a different NUMA node (same …
119 …"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or diffe…
125 …"BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the …
131 …"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or diffe…
137     "BriefDescription": "Any data cache fills from extension memory.",
143     "BriefDescription": "Any data cache fills from all types of data sources.",
149 …ative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels excep…
155 …re prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mar…
161 …ons dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-…
173 …"Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruc…
179 …"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as …
185 …"BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core fo…
191     "BriefDescription": "Software prefetch data cache fills from local L2 cache.",
197 …"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the…
203 …"BriefDescription": "Software prefetch data cache fills from cache of another CCX in the same NUMA…
209 …"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same NUMA …
215 …"BriefDescription": "Software prefetch data cache fills from cache of another CCX in a different N…
221 …"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in a different NU…
227     "BriefDescription": "Software prefetch data cache fills from extension memory.",
233     "BriefDescription": "Software prefetch data cache fills from all types of data sources.",
239     "BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
245 …"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the…
251 …"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address…
257 …"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA …
263 …"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address…
269 …"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in a different NU…
275     "BriefDescription": "Hardware prefetch data cache fills from extension memory.",
281     "BriefDescription": "Hardware prefetch data cache fills from all types of data sources.",
287 …"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations eac…
292 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
310 …"BriefDescription": "L2 cache requests: data cache state change to writable, check L2 for current …
322     "BriefDescription": "L2 cache requests: data cache shared reads.",
328     "BriefDescription": "L2 cache requests: data cache stores.",
334 …"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.…
340 …"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
364 … requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2…
388 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
394 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
400 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
406 …e to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable…
412 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
418 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
424 …  "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
430 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
436 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
442 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
448 …ine which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache).",
466 …t in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
472 … L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when…
478 …ine which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache).",
484 … L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when…
490 …hich hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data acce…
502 …cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache).",
520 …t in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
526 …s the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when…
532 …cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache).",
538 …s the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when…
544 … and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data acce…
556 …miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache).",
574 …and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
580 …ne which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when…
586 …miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache).",
592 …ne which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when…
598 …the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data acce…
610     "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
615 …"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another ca…
677 …"BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.…
688 …"BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA no…
699 …"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when th…
710 …"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when th…
721 …"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in t…
732 …"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a…
743     "BriefDescription": "Average sampled latency from all data sources.",
820     "BriefDescription": "L3 cache fill requests sourced from all data sources.",