Lines Matching +full:2 +full:a

4         "Counter": "0,1,2,3",
13 …    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
14         "Counter": "0,1,2,3",
18 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
25         "Counter": "0,1,2,3,4,5",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
35         "Counter": "0,1,2,3",
38 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44         "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
45         "Counter": "0,1,2,3",
48 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
54         "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
55         "Counter": "0,1,2,3",
58 …2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and…
64         "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
65         "Counter": "0,1,2,3",
68 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
74 …   "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
75         "Counter": "0,1,2,3",
78 …"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Pa…
85         "Counter": "0,1,2,3",
88 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)…
94         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
95         "Counter": "0,1,2,3",
99 …": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
106         "Counter": "0,1,2,3,4,5",
115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
116         "Counter": "0,1,2,3",
119 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
125         "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
126         "Counter": "0,1,2,3",
129 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
135         "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
136         "Counter": "0,1,2,3",
139 …2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB an…
145         "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
146         "Counter": "0,1,2,3",
149 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
155         "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
156         "Counter": "0,1,2,3",
159 …"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Mis…
165 …"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed …
166         "Counter": "0,1,2,3,4,5",
175         "Counter": "0,1,2,3,4,5",
184         "Counter": "0,1,2,3",
193 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction f…
194         "Counter": "0,1,2,3",
198 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instru…
205         "Counter": "0,1,2,3,4,5",
214 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
215         "Counter": "0,1,2,3",
218 …caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of…
224 …      "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
225         "Counter": "0,1,2,3",
228 …2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and…
234         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
235         "Counter": "0,1,2,3",
238 …caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of…
245         "Counter": "0,1,2,3",
254 …hat the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
255         "Counter": "0,1,2,3,4,5",