Lines Matching +full:4 +full:a
4 "Counter": "0,1,2,3,4,5,6,7",
15 "Counter": "0,1,2,3,4,5,6,7",
26 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
47 "Counter": "0,1,2,3,4,5,6,7",
57 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
58 "Counter": "0,1,2,3,4,5,6,7",
61 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
68 "Counter": "0,1,2,3,4,5",
72 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
78 "Counter": "0,1,2,3,4,5,6,7",
88 "Counter": "0,1,2,3,4,5",
99 "Counter": "0,1,2,3,4,5",
109 "Counter": "0,1,2,3,4,5,6,7",
120 "Counter": "0,1,2,3,4,5,6,7",
131 "Counter": "0,1,2,3,4,5",
141 "Counter": "0,1,2,3,4,5,6,7",
152 "Counter": "0,1,2,3,4,5",
162 "Counter": "0,1,2,3,4,5,6,7",
173 "Counter": "0,1,2,3,4,5",
183 "Counter": "0,1,2,3,4,5,6,7",
194 "Counter": "0,1,2,3,4,5",
204 "Counter": "0,1,2,3,4,5",
215 "Counter": "0,1,2,3,4,5",
226 "Counter": "0,1,2,3,4,5",
236 "Counter": "0,1,2,3,4,5,6,7",
247 "Counter": "0,1,2,3,4,5",
257 "Counter": "0,1,2,3,4,5,6,7",
268 "Counter": "0,1,2,3,4,5",
278 "Counter": "0,1,2,3,4,5,6,7",
289 "Counter": "0,1,2,3,4,5",
300 "Counter": "0,1,2,3,4,5",
310 "Counter": "0,1,2,3,4,5",
321 "Counter": "0,1,2,3,4,5",
332 "Counter": "0,1,2,3,4,5",
336 …ranch and on the execution path through which execution reached this IP. A branch misprediction…
342 "Counter": "0,1,2,3,4,5,6,7",
346 …ll the retired branch instructions that were mispredicted by the processor. A branch misprediction…
352 "Counter": "0,1,2,3,4,5",
362 "Counter": "0,1,2,3,4,5,6,7",
373 "Counter": "0,1,2,3,4,5,6,7",
384 "Counter": "0,1,2,3,4,5",
394 "Counter": "0,1,2,3,4,5,6,7",
405 "Counter": "0,1,2,3,4,5",
415 "Counter": "0,1,2,3,4,5,6,7",
426 "Counter": "0,1,2,3,4,5",
436 "Counter": "0,1,2,3,4,5,6,7",
447 "Counter": "0,1,2,3,4,5",
458 "Counter": "0,1,2,3,4,5",
469 "Counter": "0,1,2,3,4,5",
479 "Counter": "0,1,2,3,4,5,6,7",
490 "Counter": "0,1,2,3,4,5",
501 "Counter": "0,1,2,3,4,5,6,7",
505 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
512 "Counter": "0,1,2,3,4,5",
522 "Counter": "0,1,2,3,4,5",
533 "Counter": "0,1,2,3,4,5,6,7",
543 "Counter": "0,1,2,3,4,5,6,7",
552 …"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 A…
553 "Counter": "0,1,2,3,4,5,6,7",
565 …a halt state. The core enters the halt state when it is running the HLT instruction. The core freq…
572 "Counter": "0,1,2,3,4,5",
575 …a halt state. The core enters the halt state when it is running the HLT instruction. The core freq…
581 "Counter": "0,1,2,3,4,5,6,7",
584 …t distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes …
591 "Counter": "0,1,2,3,4,5,6,7",
601 "Counter": "0,1,2,3,4,5,6,7",
610 "Counter": "0,1,2,3,4,5,6,7",
621 "Counter": "0,1,2,3,4,5,6,7",
624 …ose in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructio…
633 …a halt state. The core enters the halt state when it is running the HLT instruction. This event is…
642 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
649 "Counter": "0,1,2,3,4,5",
652 …a halt state. The core enters the halt state when it is running the HLT instruction. This event is…
659 "Counter": "0,1,2,3,4,5,6,7",
662 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
671 …a halt state. The core enters the halt state when it is running the HLT instruction. The core fre…
680 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event …
687 "Counter": "0,1,2,3,4,5",
690 …a halt state. The core enters the halt state when it is running the HLT instruction. The core fre…
696 "Counter": "0,1,2,3,4,5,6,7",
699 …a halt state. The thread enters the halt state when it is running the HLT instruction. The core fr…
725 "Counter": "0,1,2,3,4,5,6,7",
755 "Counter": "0,1,2,3,4,5,6,7",
756 "CounterMask": "4",
765 "Counter": "0,1,2,3,4,5,6,7",
768 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
775 "Counter": "0,1,2,3,4,5,6,7",
784 "Counter": "0,1,2,3,4,5,6,7",
787 …"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and …
794 "Counter": "0,1,2,3,4,5,6,7",
803 …"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was …
804 "Counter": "0,1,2,3,4,5,6,7",
806 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
807 …"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS…
814 "Counter": "0,1,2,3,4,5,6,7",
824 "Counter": "0,1,2,3,4,5,6,7",
835 "Counter": "0,1,2,3,4,5,6,7",
844 "BriefDescription": "Instruction decoders utilized in a cycle",
848 …"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline…
868 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
875 "Counter": "0,1,2,3,4,5",
879 … hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general…
885 "Counter": "0,1,2,3,4,5,6,7",
889 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
895 "Counter": "0,1,2,3,4,5,6,7",
905 "Counter": "0,1,2,3,4,5,6,7",
919 …"PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples …
926 "Counter": "0,1,2,3,4,5,6,7",
930 …a byte, word, and doubleword version and string instructions can be repeated using a repetition pr…
937 "Counter": "0,1,2,3,4,5,6,7",
948 …"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear til…
949 "Counter": "0,1,2,3,4,5,6,7",
952 …"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the …
959 "Counter": "0,1,2,3,4,5,6,7",
969 "Counter": "0,1,2,3,4,5,6,7",
980 "Counter": "0,1,2,3,4,5,6,7",
990 "Counter": "0,1,2,3,4,5,6,7",
999 "Counter": "0,1,2,3,4,5,6,7",
1008 "Counter": "0,1,2,3,4,5,6,7",
1018 "Counter": "0,1,2,3,4,5,6,7",
1028 "Counter": "0,1,2,3,4,5,6,7",
1037 "Counter": "0,1,2,3,4,5,6,7",
1046 "Counter": "0,1,2,3,4,5,6,7",
1055 "Counter": "0,1,2,3,4,5,6,7",
1064 "Counter": "0,1,2,3,4,5",
1067 "EventName": "LD_BLOCKS.4K_ALIAS",
1074 …to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
1075 "Counter": "0,1,2,3,4,5",
1088 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in M…
1095 "Counter": "0,1,2,3,4,5",
1114 …"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwar…
1118 … prevented for a load operation. The most common case is a load blocked due to the address of memo…
1135 "Counter": "0,1,2,3,4,5,6,7",
1146 "Counter": "0,1,2,3,4,5,6,7",
1157 "Counter": "0,1,2,3,4,5,6,7",
1167 "Counter": "0,1,2,3,4,5,6,7",
1179 "Counter": "0,1,2,3,4,5",
1188 "Counter": "0,1,2,3,4,5",
1196 …ts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores)…
1197 "Counter": "0,1,2,3,4,5",
1206 "Counter": "0,1,2,3,4,5",
1214 …ine clears due to program modifying data (self modifying code) within 1K of a recently fetched cod…
1215 "Counter": "0,1,2,3,4,5",
1224 "Counter": "0,1,2,3,4,5,6,7",
1227 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
1234 "Counter": "0,1,2,3,4,5,6,7",
1244 "Counter": "0,1,2,3,4,5",
1255 "Counter": "0,1,2,3,4,5,6,7",
1265 "Counter": "0,1,2,3,4,5,6,7",
1275 "Counter": "0,1,2,3,4,5,6,7",
1283 …sumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from iss…
1284 "Counter": "0,1,2,3,4,5",
1287 …sumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from iss…
1294 "Counter": "0,1,2,3,4,5,6,7",
1317 …ere issued but not retired as well as the out-of-order engine recovery past a branch misprediction…
1324 "Counter": "0,1,2,3,4,5,6,7",
1335 …top-level metrics of the TMA method. This architectural event is counted on a designated fixed cou…
1342 "Counter": "0,1,2,3,4,5,6,7",
1351 …ot consumed by the backend because allocation is stalled due to a mispredicted jump or a machine c…
1352 "Counter": "0,1,2,3,4,5",
1355 …ot consumed by the backend because allocation is stalled due to a mispredicted jump or a machine c…
1361 "Counter": "0,1,2,3,4,5",
1369 … that were not consumed by the backend because allocation is stalled due to a machine clear (nuke)…
1370 "Counter": "0,1,2,3,4,5",
1379 "Counter": "0,1,2,3,4,5",
1387 …ber of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke)…
1388 "Counter": "0,1,2,3,4,5",
1397 "Counter": "0,1,2,3,4,5",
1405 "Counter": "0,1,2,3,4,5",
1413 … were not consumed by the backend due to memory reservation stalls in which a scheduler is not abl…
1414 "Counter": "0,1,2,3,4,5",
1423 "Counter": "0,1,2,3,4,5",
1432 "Counter": "0,1,2,3,4,5",
1441 "Counter": "0,1,2,3,4,5",
1450 "Counter": "0,1,2,3,4,5",
1459 "Counter": "0,1,2,3,4,5",
1467 "Counter": "0,1,2,3,4,5",
1470 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
1477 "Counter": "0,1,2,3,4,5",
1480 …ontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
1487 "Counter": "0,1,2,3,4,5",
1496 "Counter": "0,1,2,3,4,5",
1505 "Counter": "0,1,2,3,4,5",
1513 …r of issue slots every cycle that were not delivered by the frontend due to a latency related stal…
1514 "Counter": "0,1,2,3,4,5",
1523 "Counter": "0,1,2,3,4,5",
1533 "Counter": "0,1,2,3,4,5",
1542 "Counter": "0,1,2,3,4,5",
1551 "Counter": "0,1,2,3,4,5",
1569 "Counter": "0,1,2,3,4,5,6,7",
1579 "Counter": "0,1,2,3,4,5,6,7",
1589 "Counter": "0,1,2,3,4,5,6,7",
1598 "BriefDescription": "Uops executed on ports 4 and 9",
1599 "Counter": "0,1,2,3,4,5,6,7",
1602 "PublicDescription": "Number of uops dispatch to execution ports 4 and 9",
1609 "Counter": "0,1,2,3,4,5,6,7",
1619 "Counter": "0,1,2,3,4,5,6,7",
1629 "Counter": "0,1,2,3,4,5,6,7",
1639 "Counter": "0,1,2,3,4,5,6,7",
1650 "Counter": "0,1,2,3,4,5,6,7",
1661 "Counter": "0,1,2,3,4,5,6,7",
1671 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1672 "Counter": "0,1,2,3,4,5,6,7",
1673 "CounterMask": "4",
1676 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1683 "Counter": "0,1,2,3,4,5,6,7",
1694 "Counter": "0,1,2,3,4,5,6,7",
1705 "Counter": "0,1,2,3,4,5,6,7",
1715 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1716 "Counter": "0,1,2,3,4,5,6,7",
1717 "CounterMask": "4",
1720 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1727 "Counter": "0,1,2,3,4,5,6,7",
1739 "Counter": "0,1,2,3,4,5,6,7",
1751 "Counter": "0,1,2,3,4,5,6,7",
1760 "Counter": "0,1,2,3,4,5,6,7",
1770 "Counter": "0,1,2,3,4,5",
1773 …"PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops a…
1779 "Counter": "0,1,2,3,4,5,6,7",
1789 "Counter": "0,1,2,3,4,5,6,7",
1799 "Counter": "0,1,2,3,4,5",
1808 "Counter": "0,1,2,3,4,5,6,7",
1819 "Counter": "0,1,2,3,4,5,6,7",
1829 "Counter": "0,1,2,3,4,5",
1839 "Counter": "0,1,2,3,4,5",
1850 "Counter": "0,1,2,3,4,5,6,7",
1861 "Counter": "0,1,2,3,4,5,6,7",
1871 "Counter": "0,1,2,3,4,5,6,7",
1883 "Counter": "0,1,2,3,4,5,6,7",
1895 "Counter": "0,1,2,3,4,5",