Lines Matching +full:1 +full:- +full:5
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
6 "Deprecated": "1",
15 "Counter": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
19 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
26 "Counter": "0,1,2,3,4,5,6,7",
27 "CounterMask": "1",
28 "Deprecated": "1",
37 "Counter": "0,1,2,3,4,5,6,7",
38 "CounterMask": "1",
47 "Counter": "0,1,2,3,4,5,6,7",
48 "CounterMask": "1",
49 "Deprecated": "1",
58 "Counter": "0,1,2,3,4,5,6,7",
68 "Counter": "0,1,2,3,4,5",
71 "PEBS": "1",
78 "Counter": "0,1,2,3,4,5,6,7",
81 "PEBS": "1",
88 "Counter": "0,1,2,3,4,5",
89 "Deprecated": "1",
92 "PEBS": "1",
99 "Counter": "0,1,2,3,4,5",
102 "PEBS": "1",
109 "Counter": "0,1,2,3,4,5,6,7",
112 "PEBS": "1",
120 "Counter": "0,1,2,3,4,5,6,7",
123 "PEBS": "1",
131 "Counter": "0,1,2,3,4,5",
134 "PEBS": "1",
141 "Counter": "0,1,2,3,4,5,6,7",
144 "PEBS": "1",
152 "Counter": "0,1,2,3,4,5",
155 "PEBS": "1",
162 "Counter": "0,1,2,3,4,5,6,7",
165 "PEBS": "1",
173 "Counter": "0,1,2,3,4,5",
176 "PEBS": "1",
183 "Counter": "0,1,2,3,4,5,6,7",
186 "PEBS": "1",
194 "Counter": "0,1,2,3,4,5",
197 "PEBS": "1",
204 "Counter": "0,1,2,3,4,5",
205 "Deprecated": "1",
208 "PEBS": "1",
215 "Counter": "0,1,2,3,4,5",
216 "Deprecated": "1",
219 "PEBS": "1",
226 "Counter": "0,1,2,3,4,5",
229 "PEBS": "1",
236 "Counter": "0,1,2,3,4,5,6,7",
239 "PEBS": "1",
247 "Counter": "0,1,2,3,4,5",
250 "PEBS": "1",
257 "Counter": "0,1,2,3,4,5,6,7",
260 "PEBS": "1",
268 "Counter": "0,1,2,3,4,5",
271 "PEBS": "1",
278 "Counter": "0,1,2,3,4,5,6,7",
281 "PEBS": "1",
289 "Counter": "0,1,2,3,4,5",
290 "Deprecated": "1",
293 "PEBS": "1",
300 "Counter": "0,1,2,3,4,5",
303 "PEBS": "1",
310 "Counter": "0,1,2,3,4,5",
311 "Deprecated": "1",
314 "PEBS": "1",
321 "Counter": "0,1,2,3,4,5",
322 "Deprecated": "1",
325 "PEBS": "1",
332 "Counter": "0,1,2,3,4,5",
335 "PEBS": "1",
336 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
342 "Counter": "0,1,2,3,4,5,6,7",
345 "PEBS": "1",
352 "Counter": "0,1,2,3,4,5",
355 "PEBS": "1",
362 "Counter": "0,1,2,3,4,5,6,7",
365 "PEBS": "1",
372 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
373 "Counter": "0,1,2,3,4,5,6,7",
376 "PEBS": "1",
384 "Counter": "0,1,2,3,4,5",
387 "PEBS": "1",
394 "Counter": "0,1,2,3,4,5,6,7",
397 "PEBS": "1",
405 "Counter": "0,1,2,3,4,5",
408 "PEBS": "1",
414 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
415 "Counter": "0,1,2,3,4,5,6,7",
418 "PEBS": "1",
419 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
426 "Counter": "0,1,2,3,4,5",
429 "PEBS": "1",
436 "Counter": "0,1,2,3,4,5,6,7",
439 "PEBS": "1",
447 "Counter": "0,1,2,3,4,5",
448 "Deprecated": "1",
451 "PEBS": "1",
458 "Counter": "0,1,2,3,4,5",
459 "Deprecated": "1",
462 "PEBS": "1",
469 "Counter": "0,1,2,3,4,5",
472 "PEBS": "1",
479 "Counter": "0,1,2,3,4,5,6,7",
482 "PEBS": "1",
490 "Counter": "0,1,2,3,4,5",
491 "Deprecated": "1",
494 "PEBS": "1",
501 "Counter": "0,1,2,3,4,5,6,7",
504 "PEBS": "1",
505 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
512 "Counter": "0,1,2,3,4,5",
515 "PEBS": "1",
522 "Counter": "0,1,2,3,4,5",
523 "Deprecated": "1",
526 "PEBS": "1",
532 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
533 "Counter": "0,1,2,3,4,5,6,7",
536 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
542 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
543 "Counter": "0,1,2,3,4,5,6,7",
546 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
552 …"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 A…
553 "Counter": "0,1,2,3,4,5,6,7",
556 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optim…
563 "Counter": "Fixed counter 1",
565 …eason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
572 "Counter": "0,1,2,3,4,5",
581 "Counter": "0,1,2,3,4,5,6,7",
591 "Counter": "0,1,2,3,4,5,6,7",
601 "Counter": "0,1,2,3,4,5,6,7",
610 "Counter": "0,1,2,3,4,5,6,7",
611 "CounterMask": "1",
612 "EdgeDetect": "1",
621 "Counter": "0,1,2,3,4,5,6,7",
624 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
642 …1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counte…
649 "Counter": "0,1,2,3,4,5",
659 "Counter": "0,1,2,3,4,5,6,7",
662 …1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counte…
669 "Counter": "Fixed counter 1",
671 …ason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
678 "Counter": "Fixed counter 1",
687 "Counter": "0,1,2,3,4,5",
696 "Counter": "0,1,2,3,4,5,6,7",
705 "Counter": "0,1,2,3",
715 "Counter": "0,1,2,3",
716 "CounterMask": "1",
725 "Counter": "0,1,2,3,4,5,6,7",
735 "Counter": "0,1,2,3",
745 "Counter": "0,1,2,3",
746 "CounterMask": "5",
755 "Counter": "0,1,2,3,4,5,6,7",
764 …"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was no…
765 "Counter": "0,1,2,3,4,5,6,7",
767 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
768 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
775 "Counter": "0,1,2,3,4,5,6,7",
784 "Counter": "0,1,2,3,4,5,6,7",
794 "Counter": "0,1,2,3,4,5,6,7",
804 "Counter": "0,1,2,3,4,5,6,7",
814 "Counter": "0,1,2,3,4,5,6,7",
815 "CounterMask": "5",
824 "Counter": "0,1,2,3,4,5,6,7",
835 "Counter": "0,1,2,3,4,5,6,7",
845 "Counter": "0,1,2,3",
857 "PEBS": "1",
864 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
867 "PEBS": "1",
868 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
875 "Counter": "0,1,2,3,4,5",
878 "PEBS": "1",
884 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
885 "Counter": "0,1,2,3,4,5,6,7",
888 "PEBS": "1",
889 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
895 "Counter": "0,1,2,3,4,5,6,7",
898 "PEBS": "1",
905 "Counter": "0,1,2,3,4,5,6,7",
908 "PEBS": "1",
915 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
918 "PEBS": "1",
926 "Counter": "0,1,2,3,4,5,6,7",
929 "PEBS": "1",
930 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
937 "Counter": "0,1,2,3,4,5,6,7",
938 "CounterMask": "1",
939 "EdgeDetect": "1",
949 "Counter": "0,1,2,3,4,5,6,7",
959 "Counter": "0,1,2,3,4,5,6,7",
969 "Counter": "0,1,2,3,4,5,6,7",
980 "Counter": "0,1,2,3,4,5,6,7",
983 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
990 "Counter": "0,1,2,3,4,5,6,7",
999 "Counter": "0,1,2,3,4,5,6,7",
1007 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
1008 "Counter": "0,1,2,3,4,5,6,7",
1011 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
1017 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
1018 "Counter": "0,1,2,3,4,5,6,7",
1021 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
1028 "Counter": "0,1,2,3,4,5,6,7",
1037 "Counter": "0,1,2,3,4,5,6,7",
1046 "Counter": "0,1,2,3,4,5,6,7",
1055 "Counter": "0,1,2,3,4,5,6,7",
1064 "Counter": "0,1,2,3,4,5",
1065 "Deprecated": "1",
1068 "PEBS": "1",
1075 "Counter": "0,1,2,3,4,5",
1078 "PEBS": "1",
1085 "Counter": "0,1,2,3",
1095 "Counter": "0,1,2,3,4,5",
1098 "PEBS": "1",
1105 "Counter": "0,1,2,3",
1115 "Counter": "0,1,2,3",
1125 "Counter": "0,1,2,3",
1128 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
1135 "Counter": "0,1,2,3,4,5,6,7",
1136 "CounterMask": "1",
1139 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
1146 "Counter": "0,1,2,3,4,5,6,7",
1150 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
1157 "Counter": "0,1,2,3,4,5,6,7",
1160 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
1167 "Counter": "0,1,2,3,4,5,6,7",
1168 "CounterMask": "1",
1169 "EdgeDetect": "1",
1179 "Counter": "0,1,2,3,4,5",
1188 "Counter": "0,1,2,3,4,5",
1196 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
1197 "Counter": "0,1,2,3,4,5",
1206 "Counter": "0,1,2,3,4,5",
1214 …f machine clears due to program modifying data (self modifying code) within 1K of a recently fetch…
1215 "Counter": "0,1,2,3,4,5",
1223 "BriefDescription": "Self-modifying code (SMC) detected.",
1224 "Counter": "0,1,2,3,4,5,6,7",
1227 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
1234 "Counter": "0,1,2,3,4,5,6,7",
1244 "Counter": "0,1,2,3,4,5",
1247 "PEBS": "1",
1255 "Counter": "0,1,2,3,4,5,6,7",
1265 "Counter": "0,1,2,3,4,5,6,7",
1268 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
1275 "Counter": "0,1,2,3,4,5,6,7",
1283 …ue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the fr…
1284 "Counter": "0,1,2,3,4,5",
1287 …ue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the fr…
1293 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
1294 "Counter": "0,1,2,3,4,5,6,7",
1297 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
1307 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
1317 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
1324 "Counter": "0,1,2,3,4,5,6,7",
1332 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
1335 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
1341 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
1342 "Counter": "0,1,2,3,4,5,6,7",
1345 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
1352 "Counter": "0,1,2,3,4,5",
1361 "Counter": "0,1,2,3,4,5",
1370 "Counter": "0,1,2,3,4,5",
1379 "Counter": "0,1,2,3,4,5",
1388 "Counter": "0,1,2,3,4,5",
1397 "Counter": "0,1,2,3,4,5",
1405 "Counter": "0,1,2,3,4,5",
1414 "Counter": "0,1,2,3,4,5",
1423 "Counter": "0,1,2,3,4,5",
1432 "Counter": "0,1,2,3,4,5",
1441 "Counter": "0,1,2,3,4,5",
1450 "Counter": "0,1,2,3,4,5",
1459 "Counter": "0,1,2,3,4,5",
1467 "Counter": "0,1,2,3,4,5",
1477 "Counter": "0,1,2,3,4,5",
1487 "Counter": "0,1,2,3,4,5",
1496 "Counter": "0,1,2,3,4,5",
1505 "Counter": "0,1,2,3,4,5",
1514 "Counter": "0,1,2,3,4,5",
1523 "Counter": "0,1,2,3,4,5",
1533 "Counter": "0,1,2,3,4,5",
1542 "Counter": "0,1,2,3,4,5",
1551 "Counter": "0,1,2,3,4,5",
1554 "PEBS": "1",
1560 "Counter": "0,1,2,3",
1569 "Counter": "0,1,2,3,4,5,6,7",
1578 "BriefDescription": "Uops executed on port 1",
1579 "Counter": "0,1,2,3,4,5,6,7",
1582 "PublicDescription": "Number of uops dispatch to execution port 1.",
1589 "Counter": "0,1,2,3,4,5,6,7",
1599 "Counter": "0,1,2,3,4,5,6,7",
1608 "BriefDescription": "Uops executed on ports 5 and 11",
1609 "Counter": "0,1,2,3,4,5,6,7",
1612 "PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
1619 "Counter": "0,1,2,3,4,5,6,7",
1629 "Counter": "0,1,2,3,4,5,6,7",
1638 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1639 "Counter": "0,1,2,3,4,5,6,7",
1640 "CounterMask": "1",
1643 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1649 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1650 "Counter": "0,1,2,3,4,5,6,7",
1654 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1660 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1661 "Counter": "0,1,2,3,4,5,6,7",
1665 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1671 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1672 "Counter": "0,1,2,3,4,5,6,7",
1676 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1682 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1683 "Counter": "0,1,2,3,4,5,6,7",
1684 "CounterMask": "1",
1687 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1693 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1694 "Counter": "0,1,2,3,4,5,6,7",
1698 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1704 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1705 "Counter": "0,1,2,3,4,5,6,7",
1709 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1715 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1716 "Counter": "0,1,2,3,4,5,6,7",
1720 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1727 "Counter": "0,1,2,3,4,5,6,7",
1728 "CounterMask": "1",
1731 "Invert": "1",
1739 "Counter": "0,1,2,3,4,5,6,7",
1740 "CounterMask": "1",
1741 "Deprecated": "1",
1744 "Invert": "1",
1750 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1751 "Counter": "0,1,2,3,4,5,6,7",
1760 "Counter": "0,1,2,3,4,5,6,7",
1770 "Counter": "0,1,2,3,4,5",
1773 …he number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops a…
1779 "Counter": "0,1,2,3,4,5,6,7",
1789 "Counter": "0,1,2,3,4,5,6,7",
1790 "CounterMask": "1",
1799 "Counter": "0,1,2,3,4,5",
1802 "PEBS": "1",
1808 "Counter": "0,1,2,3,4,5,6,7",
1809 "CounterMask": "1",
1819 "Counter": "0,1,2,3,4,5,6,7",
1822 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1829 "Counter": "0,1,2,3,4,5",
1832 "PEBS": "1",
1838 …tion": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
1839 "Counter": "0,1,2,3,4,5",
1842 "PEBS": "1",
1850 "Counter": "0,1,2,3,4,5,6,7",
1861 "Counter": "0,1,2,3,4,5,6,7",
1871 "Counter": "0,1,2,3,4,5,6,7",
1872 "CounterMask": "1",
1875 "Invert": "1",
1883 "Counter": "0,1,2,3,4,5,6,7",
1884 "CounterMask": "1",
1885 "Deprecated": "1",
1888 "Invert": "1",
1895 "Counter": "0,1,2,3,4,5",
1898 "PEBS": "1",