x86/alderlake/frontend.json

17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
27 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
42         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
46 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
59 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
72 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
117         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
124 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n…
130 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
137 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
143 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not …
150 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this …
156         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
163 …ter an interval where the front-end delivered no uops for a period of at least 2 cycles which was …
169 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
176 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
182 …ter an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was …
189 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
195 …d after an interval where the front-end delivered no uops for a period of 32 cycles which was not …
202 …ons that are delivered to the back-end after a front-end stall of at least 32 cycles. During this …
208 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
215 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
221 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
228 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
234 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
241 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
247 …d after an interval where the front-end delivered no uops for a period of 8 cycles which was not i…
254 …ions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this …
301 …he line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk…
311 …he line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk…
449 … to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
460 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
466 …n": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not sta…
472 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
482 … to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
493 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
499 …n": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not sta…
505 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…