s390/cf_zec12/extended.json

3 		"Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 		"Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 		"Unit": "CPU-M-CF",
21 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
24 		"Unit": "CPU-M-CF",
28 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s…
31 		"Unit": "CPU-M-CF",
35 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
38 		"Unit": "CPU-M-CF",
42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
45 		"Unit": "CPU-M-CF",
49 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
52 		"Unit": "CPU-M-CF",
56 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
59 		"Unit": "CPU-M-CF",
62 		"BriefDescription": "L1D Read-only Exclusive Writes",
63 …blicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a …
66 		"Unit": "CPU-M-CF",
69 		"BriefDescription": "DTLB1 One-Megabyte Page Writes",
70 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on…
73 		"Unit": "CPU-M-CF",
77 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
80 		"Unit": "CPU-M-CF",
84 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
87 		"Unit": "CPU-M-CF",
90 		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
91 …translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for…
94 		"Unit": "CPU-M-CF",
98 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segmen…
101 		"Unit": "CPU-M-CF",
104 		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
105 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
108 		"Unit": "CPU-M-CF",
111 		"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
112 …directory write to the Level-1 Data cache directory where the returned cache line was sourced from…
115 		"Unit": "CPU-M-CF",
118 		"BriefDescription": "L1D Off-Book L3 Sourced Writes",
119 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
122 		"Unit": "CPU-M-CF",
125 		"BriefDescription": "L1D On-Book L4 Sourced Writes",
126 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
129 		"Unit": "CPU-M-CF",
132 		"BriefDescription": "L1D Off-Book L4 Sourced Writes",
133 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
136 		"Unit": "CPU-M-CF",
139 		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
140 …"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution…
143 		"Unit": "CPU-M-CF",
146 		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
147 …: "A directory write to the Level-1 Data cache directory where the returned cache line was sourced…
150 		"Unit": "CPU-M-CF",
153 		"BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
154 …directory write to the Level-1 Data cache directory where the returned cache line was sourced from…
157 		"Unit": "CPU-M-CF",
160 		"BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
161 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
164 		"Unit": "CPU-M-CF",
167 		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
168 … directory write to the Level-1 Instruction cache directory where the returned cache line was sour…
171 		"Unit": "CPU-M-CF",
174 		"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
175 …ctory write to the Level-1 Instruction cache directory where the returned cache line was sourced f…
178 		"Unit": "CPU-M-CF",
181 		"BriefDescription": "L1I Off-Book L3 Sourced Writes",
182 …directory write to the Level-1 Instruction cache directory where the returned cache line was sourc…
185 		"Unit": "CPU-M-CF",
188 		"BriefDescription": "L1I On-Book L4 Sourced Writes",
189 … directory write to the Level-1 Instruction cache directory where the returned cache line was sour…
192 		"Unit": "CPU-M-CF",
195 		"BriefDescription": "L1I Off-Book L4 Sourced Writes",
196 …directory write to the Level-1 Instruction cache directory where the returned cache line was sourc…
199 		"Unit": "CPU-M-CF",
203 …"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mo…
206 		"Unit": "CPU-M-CF",
209 		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
210 … directory write to the Level-1 Instruction cache directory where the returned cache line was sour…
213 		"Unit": "CPU-M-CF",
216 		"BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
217 …ctory write to the Level-1 Instruction cache directory where the returned cache line was sourced f…
220 		"Unit": "CPU-M-CF",
223 		"BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
224 …directory write to the Level-1 Instruction cache directory where the returned cache line was sourc…
227 		"Unit": "CPU-M-CF",
230 		"BriefDescription": "Aborted transactions in non-constrained TX mode",
231 …"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution…
234 		"Unit": "CPU-M-CF",
238 …"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mo…
241 		"Unit": "CPU-M-CF",
245 …"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mo…