s390/cf_z13/extended.json

3 		"Unit": "CPU-M-CF",
6 		"BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 		"Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 		"Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 		"Unit": "CPU-M-CF",
27 		"BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on…
31 		"Unit": "CPU-M-CF",
34 		"BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
35 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a tw…
38 		"Unit": "CPU-M-CF",
42 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
45 		"Unit": "CPU-M-CF",
49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
52 		"Unit": "CPU-M-CF",
56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
59 		"Unit": "CPU-M-CF",
63 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s…
66 		"Unit": "CPU-M-CF",
70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
73 		"Unit": "CPU-M-CF",
76 		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
77 …ranslation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays fo…
80 		"Unit": "CPU-M-CF",
84 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segm…
87 		"Unit": "CPU-M-CF",
91 …"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mo…
94 		"Unit": "CPU-M-CF",
97 		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
98 …"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-executio…
101 		"Unit": "CPU-M-CF",
105 …"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is…
108 		"Unit": "CPU-M-CF",
111 		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
112 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
115 		"Unit": "CPU-M-CF",
118 		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
119 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
122 		"Unit": "CPU-M-CF",
125 		"BriefDescription": "L1D On-Node L4 Sourced Writes",
126 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
129 		"Unit": "CPU-M-CF",
132 		"BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
133 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
136 		"Unit": "CPU-M-CF",
139 		"BriefDescription": "L1D On-Node L3 Sourced Writes",
140 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
143 		"Unit": "CPU-M-CF",
146 		"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
147 …"A directory write to the Level-1 Data cache directory where the returned cache line was sourced f…
150 		"Unit": "CPU-M-CF",
153 		"BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
154 …"A directory write to the Level-1 Data cache directory where the returned cache line was sourced f…
157 		"Unit": "CPU-M-CF",
160 		"BriefDescription": "L1D On-Drawer L3 Sourced Writes",
161 …"A directory write to the Level-1 Data cache directory where the returned cache line was sourced f…
164 		"Unit": "CPU-M-CF",
167 		"BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
168 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
171 		"Unit": "CPU-M-CF",
174 		"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
175 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
178 		"Unit": "CPU-M-CF",
181 		"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
182 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
185 		"Unit": "CPU-M-CF",
188 		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
189 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
192 		"Unit": "CPU-M-CF",
195 		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
196 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
199 		"Unit": "CPU-M-CF",
202 		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
203 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
206 		"Unit": "CPU-M-CF",
209 		"BriefDescription": "L1D On-Node Memory Sourced Writes",
210 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
213 		"Unit": "CPU-M-CF",
216 		"BriefDescription": "L1D On-Drawer Memory Sourced Writes",
217 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
220 		"Unit": "CPU-M-CF",
223 		"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
224 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
227 		"Unit": "CPU-M-CF",
230 		"BriefDescription": "L1D On-Chip Memory Sourced Writes",
231 …ion": "A directory write to the Level-1 Data cache directory where the returned cache line was sou…
234 		"Unit": "CPU-M-CF",
237 		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
238 … directory write to the Level-1 Instruction cache directory where the returned cache line was sour…
241 		"Unit": "CPU-M-CF",
244 		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
245 … directory write to the Level-1 Instruction cache directory where the returned cache line was sour…
248 		"Unit": "CPU-M-CF",
251 		"BriefDescription": "L1I On-Chip L4 Sourced Writes",
252 … directory write to the Level-1 Instruction cache directory where the returned cache line was sour…
255 		"Unit": "CPU-M-CF",
258 		"BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention",
259 … directory write to the Level-1 Instruction cache directory where the returned cache line was sour…
262 		"Unit": "CPU-M-CF",
265 		"BriefDescription": "L1I On-Node L3 Sourced Writes",
266 … directory write to the Level-1 Instruction cache directory where the returned cache line was sour…
269 		"Unit": "CPU-M-CF",
272 		"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
273 …directory write to the Level-1 Instruction cache directory where the returned cache line was sourc…
276 		"Unit": "CPU-M-CF",
279 		"BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention",
280 …directory write to the Level-1 Instruction cache directory where the returned cache line was sourc…
283 		"Unit": "CPU-M-CF",
286 		"BriefDescription": "L1I On-Drawer L3 Sourced Writes",
287 …directory write to the Level-1 Instruction cache directory where the returned cache line was sourc…
290 		"Unit": "CPU-M-CF",
293 		"BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
294 …ry write to the Level-1 Instruction cache directory where the returned cache line was sourced from…
297 		"Unit": "CPU-M-CF",
300 		"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention",
301 …ry write to the Level-1 Instruction cache directory where the returned cache line was sourced from…
304 		"Unit": "CPU-M-CF",
307 		"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes",
308 …ry write to the Level-1 Instruction cache directory where the returned cache line was sourced from…
311 		"Unit": "CPU-M-CF",
314 		"BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
315 …ory write to the Level-1 Instruction cache directory where the returned cache line was sourced fro…
318 		"Unit": "CPU-M-CF",
321 		"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention",
322 …ory write to the Level-1 Instruction cache directory where the returned cache line was sourced fro…
325 		"Unit": "CPU-M-CF",
328 		"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes",
329 …ory write to the Level-1 Instruction cache directory where the returned cache line was sourced fro…
332 		"Unit": "CPU-M-CF",
335 		"BriefDescription": "L1I On-Node Memory Sourced Writes",
336 …on": "A directory write to the Level-1 Instruction cache directory where the returned cache line w…
339 		"Unit": "CPU-M-CF",
342 		"BriefDescription": "L1I On-Drawer Memory Sourced Writes",
343 …on": "A directory write to the Level-1 Instruction cache directory where the returned cache line w…
346 		"Unit": "CPU-M-CF",
349 		"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
350 …on": "A directory write to the Level-1 Instruction cache directory where the returned cache line w…
353 		"Unit": "CPU-M-CF",
356 		"BriefDescription": "L1I On-Chip Memory Sourced Writes",
357 …": "A directory write to the Level-1 Instruction cache directory where the returned cache line was…
360 		"Unit": "CPU-M-CF",
363 		"BriefDescription": "Aborted transactions in non-constrained TX mode",
364 …"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-executio…
367 		"Unit": "CPU-M-CF",
371 …"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mo…
374 		"Unit": "CPU-M-CF",
378 …"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mo…
381 		"Unit": "CPU-M-CF",
388 		"Unit": "CPU-M-CF",