s390/cf_z10/extended.json

3 		"Unit": "CPU-M-CF",
7 …directory write to the Level-1 Instruction Cache directory where the returned cache line was sourc…
10 		"Unit": "CPU-M-CF",
14 …"A directory write to the Level-1 Data Cache directory where the installed cache line was sourced …
17 		"Unit": "CPU-M-CF",
21 …Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 ca…
24 		"Unit": "CPU-M-CF",
28 …Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that…
31 		"Unit": "CPU-M-CF",
35 …Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cach…
38 		"Unit": "CPU-M-CF",
42 …Level-1 Data Cache directory where the installed cache line was sourced from a Level-3 cache that …
45 		"Unit": "CPU-M-CF",
49 …e to the Level-1 Data Cache directory where the installed cache line was sourced from memory that …
52 		"Unit": "CPU-M-CF",
56 …o the Level-1 Instruction Cache where the installed cache line was sourced from memory that is att…
59 		"Unit": "CPU-M-CF",
62 		"BriefDescription": "L1D Read-only Exclusive Writes",
63 …Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been up…
66 		"Unit": "CPU-M-CF",
70 …cription": "A cache line in the Level-1 Instruction Cache has been invalidated by a store on the s…
73 		"Unit": "CPU-M-CF",
77 …"PublicDescription": "A translation entry has been written into the Level-1 Instruction Translatio…
80 		"Unit": "CPU-M-CF",
84 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
87 		"Unit": "CPU-M-CF",
91 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
94 		"Unit": "CPU-M-CF",
98 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segmen…
101 		"Unit": "CPU-M-CF",
104 		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
105 …"A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays …
108 		"Unit": "CPU-M-CF",
112 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
115 		"Unit": "CPU-M-CF",
119 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTL…
122 		"Unit": "CPU-M-CF",
126 		"PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache."