powerpc/power9/other.json

65     "BriefDescription": "Read-write data cache collisions"
90     "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
200     "BriefDescription": "Read-write data cache collisions"
210 …phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtrac…
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300     "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
395 …-word boundary, which causes it to require an additional slice than than what normally would be re…
430     "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
455     "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
465 …"BriefDescription": "A load-hit-load condition with Strong Address Ordering will have address comp…
470 …"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing f…
475 …-word boundary, which causes it to require an additional slice than than what normally would be re…
480 …-word boundary, which causes it to require an additional slice than than what normally would be re…
500     "BriefDescription": "TM Store (fav or non-fav) ran into conflict (failed)"
515 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
580 …"Conditional Branch Completed that had its target address predicted. Only XL-form branches set thi…
655     "BriefDescription": "Non-TM Load caused any thread to fail"
660 …-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons …
705 …"BriefDescription": "All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this t…
710 …-word boundary, which causes it to require an additional slice than than what normally would be re…
730     "BriefDescription": "32-bit constant generation"
765 …"BriefDescription": "Total number of taken branches that were incorrectly predicted as not-taken. …
825 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre…
845 …-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an addre…
890 …-word boundary, which causes it to require an additional slice than than what normally would be re…
1000 …NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-…
1080     "BriefDescription": "L2 Castouts - Modified (M,Mu,Me)"
1095 …"BriefDescription": "Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalida…
1135 …"BriefDescription": "L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip…
1145 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
1160 …-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision …
1215 …-induced conflict occurred in Suspended state, due to one of the following: a store to a storage l…
1225 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1250 …"BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EX…
1265 …-word boundary, which causes it to require an additional slice than than what normally would be re…
1275 …"BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EX…
1290     "BriefDescription": "L2 Castouts - Shared (Tx,Sx)"
1295 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1300     "BriefDescription": "All successful D-Side Load dispatches that were an L2 miss for this thread"
1325     "BriefDescription": "Instruction SLB Miss - Total of all segment sizes"
1355     "BriefDescription": "Non-TM Store caused any thread to fail"
1370 …"BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) fo…
1380 …o the Target Address Prediction from the Count Cache or Link Stack.  Only XL-form branches that re…
1385 …"BriefDescription": "BTAC thinks branch will be taken but it is either predicted not-taken by the …
1405     "BriefDescription": "All D-side store dispatch attempts for this thread"
1410 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to reason …
1430 …"BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatche…
1440     "BriefDescription": "Read-write data cache collisions"
1445     "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread"
1480 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
1500 …"BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) fo…
1505 …"BriefDescription": "Valid when first beat of data comes in for an I-side fetch where data came fr…
1510     "BriefDescription": "Read-write data cache collisions"
1530 …"BriefDescription": "Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared s…
1540     "BriefDescription": "32-bit displacement D-form and 16-bit displacement X-form"
1555 …d. I-form branches do not set this event.  In addition, B-form branches which do not use the BHT d…
1595 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre…
1635 …"BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed du…
1675 …"BriefDescription": "TM aborted because a conflict occurred with a non-transactional access by ano…
1715 …"BriefDescription": "I-side L2 MRU touch sent to L2 for this thread I-side L2 MRU touch commands s…
1720     "BriefDescription": "Store-Hit-Load Table Entry Created"
1740     "BriefDescription": "L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)"
1770 …"BriefDescription": "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it w…
1780     "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled"
1785     "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits"
1805 …  "BriefDescription": "All successful D-Side Store dispatches that were an L2 miss for this thread"
1810 …"BriefDescription": "Prefetch stream allocated in the Ultra conservative phase by either the hardw…
1850     "BriefDescription": "TM Store (fav or non-fav) caused another thread to fail"
1955 …escription": "L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)"
1960 …"BriefDescription": "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due …
1990     "BriefDescription": "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)"
2020 …es of this, one example is store and reload are lined up such that a store-hit-reload scenario exi…
2030 …"BriefDescription": "Quad-word loads (lq) are considered atomic because they always span at least …
2075 …-word boundary, which causes it to require an additional slice than than what normally would be re…
2095 …  "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread"
2140 …"BriefDescription": "L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group…
2150 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
2200     "BriefDescription": "All successful D-side store dispatches for this thread"
2205 …"BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatche…
2240     "BriefDescription": "All successful D-side store dispatches for this thread (L2 miss + L2 hits)"
2260 …  "BriefDescription": "CLB (control logic block - indicates quadword fetch block) Hold: Any Reason"
2330 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to address…