powerpc/power9/other.json

45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load"
60 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea…
135 …n an enabled section of the Load Monitored region.  This event, therefore, should not occur if the…
145 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load"
170     "BriefDescription": "Load tm hit in L1"
205 … to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
225 …cles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load"
230     "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load"
235 …  "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated"
255 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load"
305 …"BriefDescription": "If a load that has already returned data and has to relaunch for any reason t…
320 …e was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load"
335     "BriefDescription": "Load tm L1 miss"
350 …s to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load"
385 …dified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load"
395 …Load instructions whose data crosses a double-word boundary, which causes it to require an additio…
430     "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
435 …ocessor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load"
465 …"BriefDescription": "A load-hit-load condition with Strong Address Ordering will have address comp…
475 …Load instructions whose data crosses a double-word boundary, which causes it to require an additio…
495 …ion": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load"
520 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea…
530     "BriefDescription": "Load tm L1 miss"
535     "BriefDescription": "LS1 finished load vector op"
550 …er of load instructions that finished with an L1 miss. Note that even if a load spans multiple sli…
565 …from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load"
590     "BriefDescription": "RC retries on PB for any load from core (excludes DCBFs)"
605 …"BriefDescription": "A demand load referenced a line in an active prefetch stream. The stream coul…
620 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
630 …ocessor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load"
640 …n": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load"
645 …"BriefDescription": "Number of times a load or store instruction was unable to launch/relaunch bec…
655     "BriefDescription": "Non-TM Load caused any thread to fail"
685 …"BriefDescription": "L3 load prefetch, sourced from a hardware or software stream, was sent to the…
735 …e was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load"
810 … "Duration in cycles to reload from a location other than the local core's L2 due to a marked load"
830 …"BriefDescription": "L3 load prefetch, sourced from a software prefetch stream, was sent to the ne…
840 …s reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
870 …efDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load"
890 …Load instructions whose data crosses a double-word boundary, which causes it to require an additio…
905 …ription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load"
910 …cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load"
1000 …tall because the NTF instruction was a load that was held in LSAQ (load-store address queue) becau…
1015 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
1035 …fDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load"
1060 …ycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load"
1070     "BriefDescription": "Load tm hit in L1"
1085 …"BriefDescription": "Number of times a load or store instruction was unable to launch/relaunch bec…
1140 …n an enabled section of the Load Monitored region.  This event, therefore, should not occur if the…
1180 …was reloaded from a memory location including L4 from local remote or distant due to a marked load"
1195 …n": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load"
1200     "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load"
1205 …cles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load"
1225 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1265 …Load instructions whose data crosses a double-word boundary, which causes it to require an additio…
1295 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1300     "BriefDescription": "All successful D-Side Load dispatches that were an L2 miss for this thread"
1305 …e was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load"
1315 …cles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load"
1340     "BriefDescription": "Number of vector load instructions completed"
1350     "BriefDescription": "LS2 finished load vector op"
1390 …n an enabled section of the Load Monitored region.  This event, therefore, should not occur if the…
1415 …"BriefDescription": "A demand load referenced a line in an active strided prefetch stream. The str…
1460     "BriefDescription": "Load tm L1 miss"
1475     "BriefDescription": "Load tm hit in L1"
1495 …The processor's data cache was reloaded from local core's L3 without conflict due to a marked load"
1525 …The processor's data cache was reloaded from local core's L2 without conflict due to a marked load"
1545 … to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load"
1580 …s reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load"
1590 …n an enabled section of the Load Monitored region.  This event, therefore, should not occur if the…
1625 …tial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst …
1670     "BriefDescription": "Load tm L1 miss"
1710 …he was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load"
1720     "BriefDescription": "Store-Hit-Load Table Entry Created"
1770 …"BriefDescription": "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it w…
1780     "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled"
1845 …ssor's data cache was reloaded from a location other than the local core's L2 due to a marked load"
1900 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
1905 …ruction was flushed because of a sequential load/store consistency.  If a load or store hits on an…
1915 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
1945 …ription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load"
1970 …es to reload from a memory location including L4 from local remote or distant due to a marked load"
1975     "BriefDescription": "Load tm hit in L1"
1990     "BriefDescription": "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)"
2000     "BriefDescription": "LS0 finished load vector op"
2020 …including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either s…
2030 …t 2 slices.  If a snoop or store from another thread changes the data the load is accessing betwee…
2055 …dified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load"
2090 …h but Real Address match.  If the data has not yet been returned for this load, the instruction wi…
2125     "BriefDescription": "All L1 D cache load references counted at finish, gated by reject"
2155     "BriefDescription": "TM Load (fav) caused another thread to fail"
2220 …e was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load"
2295     "BriefDescription": "LS3 finished load vector op"