powerpc/power9/other.json

45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
65     "BriefDescription": "Read-write data cache collisions"
90     "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d…
145 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
200     "BriefDescription": "Read-write data cache collisions"
255 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
260     "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted"
270     "BriefDescription": "L3 CO to memory port 0 with or without data"
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300     "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
320 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
395 …-word boundary, which causes it to require an additional slice than than what normally would be re…
430     "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
435 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
455     "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
465 …"BriefDescription": "A load-hit-load condition with Strong Address Ordering will have address comp…
470 …"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing f…
475 …-word boundary, which causes it to require an additional slice than than what normally would be re…
480 …-word boundary, which causes it to require an additional slice than than what normally would be re…
485     "BriefDescription": "L3 CO received retry port 2 (memory only), every retry counted"
495 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
500     "BriefDescription": "TM Store (fav or non-fav) ran into conflict (failed)"
515 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
565 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
580 …"Conditional Branch Completed that had its target address predicted. Only XL-form branches set thi…
630 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
655     "BriefDescription": "Non-TM Load caused any thread to fail"
660 …-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons …
675     "BriefDescription": "L3 CO to memory port 1 with or without data"
705 …"BriefDescription": "All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this t…
710 …-word boundary, which causes it to require an additional slice than than what normally would be re…
730     "BriefDescription": "32-bit constant generation"
735 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
765 …"BriefDescription": "Total number of taken branches that were incorrectly predicted as not-taken. …
825 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre…
840 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
845 …-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an addre…
870 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked …
890 …-word boundary, which causes it to require an additional slice than than what normally would be re…
1000 …NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-…
1005 …"BriefDescription": "L3 CO of line in Mep state (includes casthrough to memory).  The Mepf state i…
1015 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
1075 …"BriefDescription": "L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come …
1080     "BriefDescription": "L2 Castouts - Modified (M,Mu,Me)"
1095 …"BriefDescription": "Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalida…
1105 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit witho…
1135 …"BriefDescription": "L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip…
1145 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
1160 …-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision …
1180 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f…
1185     "BriefDescription": "L2 CO miss"
1190 …"BriefDescription": "CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample p…
1210 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data…
1215 …-induced conflict occurred in Suspended state, due to one of the following: a store to a storage l…
1225 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1250 …"BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EX…
1265 …-word boundary, which causes it to require an additional slice than than what normally would be re…
1270     "BriefDescription": "L2 CO hits"
1275 …"BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EX…
1290     "BriefDescription": "L2 Castouts - Shared (Tx,Sx)"
1295 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1300     "BriefDescription": "All successful D-Side Load dispatches that were an L2 miss for this thread"
1305 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
1325     "BriefDescription": "Instruction SLB Miss - Total of all segment sizes"
1330     "BriefDescription": "L3 CO received retry port 1 (memory only), every retry counted"
1355     "BriefDescription": "Non-TM Store caused any thread to fail"
1370 …"BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) fo…
1375 …nuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU us…
1380 …o the Target Address Prediction from the Count Cache or Link Stack.  Only XL-form branches that re…
1385 …"BriefDescription": "BTAC thinks branch will be taken but it is either predicted not-taken by the …
1405     "BriefDescription": "All D-side store dispatch attempts for this thread"
1410 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to reason …
1430 …"BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatche…
1440     "BriefDescription": "Read-write data cache collisions"
1445     "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread"
1450     "BriefDescription": "L3 CO to L3.1 (LCO) port 1 with or without data"
1480 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
1485 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1490     "BriefDescription": "CO dispatch failed due to all CO machines being busy"
1495 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict…
1500 …"BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) fo…
1505 …"BriefDescription": "Valid when first beat of data comes in for an I-side fetch where data came fr…
1510     "BriefDescription": "Read-write data cache collisions"
1525 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict…
1530 …"BriefDescription": "Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared s…
1540     "BriefDescription": "32-bit displacement D-form and 16-bit displacement X-form"
1550 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1555 …d. I-form branches do not set this event.  In addition, B-form branches which do not use the BHT d…
1580 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch…
1595 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre…
1600     "BriefDescription": "Rotating sample of 16 CI or CO actives"
1635 …-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an…
1675 …ion": "TM aborted because a conflict occurred with a non-transactional access by another processor"
1700     "BriefDescription": "Lifetime, sample of CO machine 0 valid"
1710 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
1715 …"BriefDescription": "I-side L2 MRU touch sent to L2 for this thread I-side L2 MRU touch commands s…
1720     "BriefDescription": "Store-Hit-Load Table Entry Created"
1740     "BriefDescription": "L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)"
1755 …"BriefDescription": "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM…
1770 …"BriefDescription": "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it w…
1780     "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled"
1785     "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits"
1805 …  "BriefDescription": "All successful D-Side Store dispatches that were an L2 miss for this thread"
1845 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
1850     "BriefDescription": "TM Store (fav or non-fav) caused another thread to fail"
1875 …"BriefDescription": "L3 CO to L3.1 OR of port 0 and 1 (lossy = may undercount if two cresps come i…
1915 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
1955 …escription": "L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)"
1960 …"BriefDescription": "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due …
1990     "BriefDescription": "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)"
2020 …es of this, one example is store and reload are lined up such that a store-hit-reload scenario exi…
2030 …"BriefDescription": "Quad-word loads (lq) are considered atomic because they always span at least …
2055 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a…
2075 …-word boundary, which causes it to require an additional slice than than what normally would be re…
2095 …  "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread"
2140 …"BriefDescription": "L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group…
2150 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
2165     "BriefDescription": "L3 CO received retry port 0 (memory only), every retry counted"
2185     "BriefDescription": "L3 CO to L3.1 (LCO) port 0 with or without data"
2200     "BriefDescription": "All successful D-side store dispatches for this thread"
2205 …"BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatche…
2220 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
2240     "BriefDescription": "All successful D-side store dispatches for this thread (L2 miss + L2 hits)"
2260 …  "BriefDescription": "CLB (control logic block - indicates quadword fetch block) Hold: Any Reason"
2330 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to address…