powerpc/power9/metrics.json

8         "BriefDescription": "Count cache branch misprediction per instruction",
44 …"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution p…
50 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and wa…
56 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
68 …"BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating P…
134 …"BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to t…
140 …"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction…
146 …"BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response fro…
152 …"BriefDescription": "Finish stall because the next to finish instruction suffered an ERAT miss and…
163 …"BriefDescription": "Finish stall because the NTF instruction was a load or store that suffered a …
169 …ch the NTC instruction is not allowed to complete because it was interrupted by ANY exception, whi…
187 …"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of…
193 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi…
205 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p…
211 …    "BriefDescription": "Instruction Completion Table empty for this thread due to branch mispred",
217 …"BriefDescription": "Instruction Completion Table empty for this thread due to Icache Miss and bra…
223         "BriefDescription": "Instruction Completion Table other stalls",
235 …"BriefDescription": "Instruction Completion Table empty for this thread due to dispatch holds beca…
241 …"BriefDescription": "Instruction Completion Table empty for this thread due to dispatch hold on th…
253         "BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch",
259 …"BriefDescription": "the NTC instruction is being held at dispatch because it is a tbegin instruct…
271 …"BriefDescription": "Instruction Completion Table empty for this thread due to icache misses that …
277 …"BriefDescription": "Instruction Completion Table empty for this thread due to icache misses that …
283         "BriefDescription": "Instruction Completion Table empty for this thread due to Icache Miss",
294 … "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied",
300 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor…
306 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and…
312 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its …
318 …"BriefDescription": "Finish stall because the NTF instruction was a load that was held in LSAQ bec…
335 …instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ…
346 …"BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or …
352 …e. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to c…
358 …"BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an…
370         "BriefDescription": "Completion stall by LSU instruction",
394 …"BriefDescription": "Number of cycles the Instruction Completion Table has no itags assigned to th…
400 …"BriefDescription": "Finish stall because the NTF instruction was one that must finish at dispatch…
406 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This e…
418 …escription": "The NTC instruction is being held at dispatch because it lost arbitration onto the i…
424 …"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in t…
430 …"BriefDescription": "The NTC instruction is being held at dispatch during regular pipeline cycles,…
448 …"BriefDescription": "Finish stall because the NTF instruction was a paste waiting for response fro…
454 …"BriefDescription": "Finish stall because the NTF instruction was issued to the Permute execution …
460         "BriefDescription": "Run cycles per run instruction",
477 …"BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB",
489 …"BriefDescription": "Finish stall because the NTF instruction was a store that was held in LSAQ be…
506         "BriefDescription": "Nothing completed and Instruction Completion Table not empty",
512 …"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from…
518 …"BriefDescription": "Finish stall because the next to finish instruction was a store waiting on da…
524 …Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. …
530 …"BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencie…
536 … because the NTF instruction was a store waiting for the next relaunch opportunity after an intern…
542 …"BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting resp…
554 …"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response fro…
566 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…
572 …"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction…
583 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi…
595 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin…
655 …loads that came from the L3 and were brought into the L3 by a prefetch, per instruction completed",
697         "BriefDescription": "Percentage of L1 demand load misses per run instruction",
895         "BriefDescription": "Branch Mispredict flushes per instruction",
901         "BriefDescription": "Cycles per instruction",
943         "BriefDescription": "Percentage of L1 store misses per run instruction",
955         "BriefDescription": "L2 Instruction Miss Rate (per instruction)(%)",
961         "BriefDescription": "L2 dmand Load Miss Rate (per run instruction)(%)",
967         "BriefDescription": "L2 PTEG Miss Rate (per run instruction)(%)",
973         "BriefDescription": "L3 Instruction Miss Rate (per instruction)(%)",
979         "BriefDescription": "L3 demand Load Miss Rate (per run instruction)(%)",
985         "BriefDescription": "L3 PTEG Miss Rate (per run instruction)(%)",
997         "BriefDescription": "Instruction dispatch-to-completion ratio",
1099         "BriefDescription": "Instruction Cache Miss Rate (Per run Instruction)(%)",
1417 …   "BriefDescription": "L1 Prefetches issued by the prefetch machine per instruction (per thread)",
1423         "BriefDescription": "DERAT Miss Rate (per run instruction)(%)",
1679         "BriefDescription": "% Branches per instruction",
1684         "BriefDescription": "Cycles in which at least one instruction completes in this thread",
1694         "BriefDescription": "Percentage Cycles at least one instruction dispatched",
1699         "BriefDescription": "Cycles per instruction group",
1749 …"BriefDescription": "Cycles in which the oldest instruction is finished and ready to complete for …
1794         "BriefDescription": "Percent of instruction reads out of all L2 commands",
1839         "BriefDescription": "PCT instruction loads",
1854         "BriefDescription": "PCT instruction stores",