powerpc/power9/marked.json

5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n…
15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at…
35 …cription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conf…
65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o…
75     "BriefDescription": "Vector FP instruction completed"
80 …Description": "The processor's Instruction cache was reloaded from local core's L2 without conflic…
85 …ription": "The processor's Instruction cache was reloaded from a location other than the local cor…
90 …ch the NTC instruction is not allowed to complete because it was interrupted by ANY exception, whi…
115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
120 …: "The processor's Instruction cache was reloaded from another chip's memory on the same Node or G…
135 …"BriefDescription": "Finish stall because the NTF instruction was issued to the Permute execution …
140 …aded into the TLB from a location other than the local core's L2 due to a instruction side request"
155 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
170 …om local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request"
175     "BriefDescription": "Marked instruction issued"
195 …: "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on…
215 …"BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response fro…
280 …: "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Gr…
285 …"BriefDescription": "The NTC instruction is being held at dispatch during regular pipeline cycles,…
310 …riefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache d…
320 …ption": "The processor's Instruction cache was reloaded from local core's L2 with load hit store c…
330 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
335 …TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request"
345     "BriefDescription": "marked instruction completed"
355 … "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 o…
360 …"BriefDescription": "Finish stall because the NTF instruction was one that must finish at dispatch…
380 …": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on …
390     "BriefDescription": "The thread has dispatched a randomly sampled marked instruction"
410 …"BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to t…
420     "BriefDescription": "Branch Instruction completed"
510     "BriefDescription": "SP instruction completed"
555 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
560 …"A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request"
565 …"A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request"
575     "BriefDescription": "marked Instruction finish timeout (instruction lost)"
585     "BriefDescription": "marked instruction finished"
605 …B with Modified (M) data from another core's L2 on the same chip due to a instruction side request"
610 …"BriefDescription": "Finish stall because the NTF instruction was a paste waiting for response fro…