powerpc/power9/marked.json

20 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side requ…
25 …e was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load"
35 …Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction f…
55     "BriefDescription": "Completion stall due to ntc flush"
60 …"A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data si…
70 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data si…
80 …sor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction f…
85 …truction cache was reloaded from a location other than the local core's L3 due to a instruction fe…
95 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data si…
100 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side requ…
105     "BriefDescription": "DL1 reloaded due to Demand Load"
110 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load"
120 …as reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction f…
130 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a…
140 …try was loaded into the TLB from a location other than the local core's L2 due to a instruction si…
155 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
170 …the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction si…
180 …che was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load"
185 …e was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load"
190 …cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load"
195 …as reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction f…
210 …: "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data si…
220 …try was loaded into the TLB from a location other than the local core's L3 due to a marked data si…
240 …dified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load"
245 …was reloaded from a memory location including L4 from local remote or distant due to a demand load"
260 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked …
280 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction f…
290 …: "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side requ…
310 … processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction f…
320 …ction cache was reloaded from local core's L2 with load hit store conflict due to an instruction f…
330 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f…
335 … into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction si…
340 …ssor's data cache was reloaded from a location other than the local core's L3 due to a demand load"
350 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
355 … reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction f…
380 … was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction f…
415 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data…
440 … Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side requ…
460 …ded either shared or modified data from another core's L2/L3 on the same chip due to a demand load"
475 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
480 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
490 …was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load"
520 …"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked l…
540 …"BriefDescription": "Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR…
550 …nto the TLB with Modified (M) data from another core's L3 on the same chip due to a data side requ…
555 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f…
560 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a inst…
565 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a inst…
590 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data si…
605 …nto the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction si…