powerpc/power9/frontend.json

5 …B with Modified (M) data from another core's L3 on the same chip due to a instruction side request"
15 …aded into the TLB from a location other than the local core's L3 due to a instruction side request"
20 …"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in t…
25 …instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ…
40 … or the original scope was System and it should have been smaller. Counts for an instruction fetch"
45     "BriefDescription": "Marked Instruction RC dispatched in L2"
60 … Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch"
70 …Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. …
75 …s finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an ad…
80 …e. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to c…
85 …"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from…
90     "BriefDescription": "Completion stall by LSU instruction"
115 …TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request"
140 …"BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an…
165 …"BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencie…
175 …tion": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch"
220 …"BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to …
225 …"BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrup…
240     "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet"
245 …ry was loaded into the TLB from local core's L3 without conflict due to a instruction side request"
255 …"BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting resp…
265 …om local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request"
270 …fDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch"
280 …'s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request"
285 …"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch"
290 …"BriefDescription": "Finish stall because the next to finish instruction was a store waiting on da…
315 …with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request"
320 … because the NTF instruction was a store waiting for the next relaunch opportunity after an intern…
345 …"BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or …
355 …th Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request"