Lines Matching +full:system +full:- +full:on +full:- +full:chip
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
36 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w…
41 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a…
42 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w…
59 …"BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,…
60 …n": "Initial and Final Pump Scope and data sourced across this scope was system pump for all data …
65 …n": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) …
66 …system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Sco…
71 …"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group…
72 …"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial P…
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
125 …"BriefDescription": "Conditional Branch Completed on BR0 (1st branch in group) in which the HW pre…
131 …"BriefDescription": "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW pre…
143 …"BriefDescription": "Conditional Branch Completed on BR0 that used the Count Cache for Target Pred…
149 …"BriefDescription": "Conditional Branch Completed on BR1 that used the Count Cache for Target Pred…
161 …on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-for…
167 …on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-for…
179 …"BriefDescription": "Conditional Branch Completed on BR0 that used the Link Stack for Target Predi…
185 …"BriefDescription": "Conditional Branch Completed on BR1 that used the Link Stack for Target Predi…
197 …BriefDescription": "Conditional Branch Completed on BR0 that had its target address predicted. Onl…
203 …BriefDescription": "Conditional Branch Completed on BR1 that had its target address predicted. Onl…
215 …d on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-for…
221 …d on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-for…
359 "BriefDescription": "IFU Finished a (non-branch) instruction",
365 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for either de…
366 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
371 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
372 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
377 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
378 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
383 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
384 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
389 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
390 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…
401 …ta cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either…
402 …ta cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either…
407 …data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either…
408 …data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either…
431 …ata cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to ei…
432 …ata cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to ei…
449 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either…
450 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either…
455 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either…
456 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either…
461 …ta cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either…
462 …ta cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either…
467 …data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either…
468 …data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either…
485 …ata cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to ei…
486 …ata cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to ei…
497 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
498 …"PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due t…
503 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to e…
504 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to …
515 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
516 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
521 …s reloaded either shared or modified data from another core's L2/L3 on the same chip due to either…
522 …s reloaded either shared or modified data from another core's L2/L3 on the same chip due to either…
527 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
528 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
533 … reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
534 … reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
539 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…
540 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same N…
545 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
546 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…
558 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w…
563 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for e…
564 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w…
581 …"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for either …
582 …n": "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand …
587 …n": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) …
588 …system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Sco…
593 …"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group…
594 …"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial P…
599 …ta cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a dema…
600 …ta cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either…
605 …data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a dema…
606 …data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either…
611 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a dema…
612 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either…
617 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a dema…
618 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either…
623 …ta cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a dema…
624 …ta cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either…
629 …data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a dema…
630 …data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either…
683 "BriefDescription": "BCD->DPD opcode finish (denbcd, denbcdq)",
755 …s loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data…
761 …was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data…
779 …aded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data…
785 …loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data…
791 …s loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data…
797 …was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data…
803 …"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing f…
810 …"PublicDescription": "Cycles No room in EATSet on bank conflict and case where no ibuffers availab…
1001 …"BriefDescription": "Group dispatched on a merged GCT empty. GCT entries can be merged only within…
1025 …"BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to Issue q …
1031 …"BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to Mapper f…
1037 "BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to sync",
1043 …"BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to SRQ full…
1061 "BriefDescription": "GCT Utilization 11-14 entries",
1067 "BriefDescription": "GCT Utilization 15-17 entries",
1079 "BriefDescription": "GCT Utilization 1-2 entries",
1085 "BriefDescription": "GCT Utilization 3-6 entries",
1091 "BriefDescription": "GCT Utilization 7-10 entries",
1097 "BriefDescription": "Group experienced non-speculative branch redirect",
1098 "PublicDescription": "Group experienced Non-speculative br mispredicct"
1115 "BriefDescription": "Group experienced non-speculative I cache miss",
1116 "PublicDescription": "Group experi enced Non-specu lative I cache miss"
1229 "BriefDescription": "L2 touch to update MRU on a line",
1235 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for instructi…
1236 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
1241 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
1242 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
1247 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
1248 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
1253 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
1254 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
1259 …tion": "The processor's Instruction cache was reloaded from another chip's memory on the same Node…
1260 …tion": "The processor's Instruction cache was reloaded from another chip's memory on the same Node…
1271 …on cache was reloaded with Modified (M) data from another core's L2 on the same chip due to instru…
1272 …on cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either…
1277 …tion cache was reloaded with Shared (S) data from another core's L2 on the same chip due to instru…
1278 …tion cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either…
1301 …ion cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to i…
1302 …ion cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to e…
1319 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to instru…
1320 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either…
1325 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to instru…
1326 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either…
1331 …on cache was reloaded with Modified (M) data from another core's L3 on the same chip due to instru…
1332 …on cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either…
1337 …tion cache was reloaded with Shared (S) data from another core's L3 on the same chip due to instru…
1338 …tion cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either…
1355 …ion cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to i…
1356 …ion cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to e…
1367 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache…
1368 …"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cach…
1373 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d…
1374 …"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's Memory …
1385 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
1386 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
1391 …s reloaded either shared or modified data from another core's L2/L3 on the same chip due to instru…
1392 …s reloaded either shared or modified data from another core's L2/L3 on the same chip due to either…
1397 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
1398 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
1403 … reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
1404 … reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
1409 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the …
1410 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the…
1415 …tion": "The processor's Instruction cache was reloaded from another chip's memory on the same Node…
1416 …tion": "The processor's Instruction cache was reloaded from another chip's memory on the same Node…
1428 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w…
1433 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for i…
1434 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w…
1451 …"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for instruc…
1452 …n": "Initial and Final Pump Scope and data sourced across this scope was system pump for an instru…
1457 …n": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) …
1458 …system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Sco…
1463 …"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group…
1464 …"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial P…
1475 …on cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an ins…
1476 …on cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either…
1481 …tion cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an ins…
1482 …tion cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either…
1487 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an ins…
1488 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either…
1493 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an ins…
1494 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either…
1499 …on cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an ins…
1500 …on cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either…
1505 …tion cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an ins…
1506 …tion cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either…
1523 …s loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a inst…
1529 …was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a inst…
1547 …aded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a inst…
1553 …loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a inst…
1559 …s loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a inst…
1565 …was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a inst…
1571 …"BriefDescription": "valid when first beat of data comes in for an i-side fetch where data came fr…
1703 "BriefDescription": "RC requests that were local on chip pump attempts",
1709 "BriefDescription": "RC requests that were on Node Pump attempts",
1715 "BriefDescription": "RC retries on PB for any store from core",
1721 "BriefDescription": "All successful D-side store dispatches for this thread",
1727 "BriefDescription": "All successful D-side store dispatches for this thread that were L2 Miss",
1799 "BriefDescription": "L3 Prefetch from Off chip cache",
1805 "BriefDescription": "L3 Prefetch from Off chip memory",
1811 "BriefDescription": "L3 Prefetch from On chip cache",
1817 "BriefDescription": "L3 Prefetch from On chip memory",
2003 "BriefDescription": "LS0 Non-cachable Loads counted at finish",
2004 "PublicDescription": "LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads"
2033 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
2034 …"PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is…
2093 "BriefDescription": "LS1 Non-cachable Loads counted at finish",
2094 "PublicDescription": "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads"
2123 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
2124 …"PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is…
2207 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
2208 …"PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is…
2291 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
2292 …"PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is…
2309 "BriefDescription": "Erat miss due to prefetch, on either pipe",
2315 "BriefDescription": "Unaligned Store Flush on either pipe",
2321 "BriefDescription": "Cycles when four tablewalks pending on this thread",
2322 "PublicDescription": "Cycles when four tablewalks pending on this thread42"
2339 "BriefDescription": "Software L1 Prefetches, including SW Transient Prefetches, on both pipes",
2345 "BriefDescription": "FPU loads only on LS2/LS3 ie LU0/LU1",
2351 "BriefDescription": "Vector loads can issue only on LS2/LS3",
2363 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2381 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2411 "BriefDescription": "count at finish so can return only on ls0 or ls1",
2417 "BriefDescription": "Non-cachable Stores sent to nest",
2418 "PublicDescription": "Non-cachable Stores sent to nest42"
2441 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2477 "BriefDescription": "Store reject on either pipe",
2483 "BriefDescription": "Cycles when two tablewalks pending on this thread",
2484 "PublicDescription": "Cycles when two tablewalks pending on this thread42"
2489 …eaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out",
2501 "BriefDescription": "IFU non-branch finished",
2502 "PublicDescription": "IFU non-branch marked instruction finished"
2507 …ta cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a mark…
2513 …n in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a mark…
2519 …data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a mark…
2525 …ion in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a mark…
2531 …ache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a mark…
2537 … cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a mark…
2543 … cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a mark…
2549 …in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a mark…
2555 …ta cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a mark…
2561 …n in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a mark…
2567 …data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a mark…
2573 …ion in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a mark…
2585 …s loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a mark…
2591 …was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a mark…
2609 …aded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a mark…
2615 …loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a mark…
2621 …s loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a mark…
2627 …was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a mark…
2904 "PublicDescription": "Cycles run latch is set and core is in SMT2-shared mode"
2909 "BriefDescription": "Cycles run latch is set and core is in SMT2-split mode",
2927 "BriefDescription": "Store-Hit-Load Table Entry Created",
2933 "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled",
2939 …"BriefDescription": "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to …
3023 "BriefDescription": "Cycles group completed on both completion slots by any thread",
3239 "BriefDescription": "Move to/from FPSCR type instruction issued on Pipe 0",
3257 "BriefDescription": "Double Precision scalar instruction issued on Pipe0",
3281 "BriefDescription": "FPU store (SP or DP) issued on Pipe0",
3287 "BriefDescription": "Double Precision vector instruction issued on Pipe0",
3389 "BriefDescription": "Move to/from FPSCR type instruction issued on Pipe 0",
3407 "BriefDescription": "Double Precision scalar instruction issued on Pipe1",
3431 "BriefDescription": "FPU store (SP or DP) issued on Pipe1",
3437 "BriefDescription": "Double Precision vector instruction issued on Pipe1",