Lines Matching full:due
77 …"BriefDescription": "Read blocked due to interleave conflict. The ifar logic will detect an interl…
95 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Count Cache Tar…
101 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the BHT Direction P…
107 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Link Stack Targ…
113 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Target Address …
251 "BriefDescription": "Completion stall due to IFU",
257 "BriefDescription": "Completion stall due to CO q full",
263 "BriefDescription": "completion stall due to flush by own thread",
269 "BriefDescription": "Completion stall due to mem ECC delay",
275 "BriefDescription": "Completion stall due to nop",
281 "BriefDescription": "Completion stall due to ntcg flush",
282 "PublicDescription": "Completion stall due to reject (load hit store)"
287 "BriefDescription": "Completion stall due to LSU reject",
293 "BriefDescription": "Completion stall due to reject (load hit store)",
299 "BriefDescription": "Completion stall due to LSU reject LMQ full",
305 "BriefDescription": "Completion stall due to VSU scalar instruction",
311 "BriefDescription": "Completion stall due to VSU scalar long latency instruction",
323 "BriefDescription": "Completion stall due to VSU vector instruction",
329 "BriefDescription": "Completion stall due to VSU vector long instruction",
335 "BriefDescription": "Completion stall due to VSU instruction",
371 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand lo…
372 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only dema…
377 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand lo…
378 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only dema…
383 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either demand lo…
384 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only dema…
389 …as reloaded from another chip's memory on the same Node or Group (Distant) due to either demand lo…
390 …as reloaded from another chip's memory on the same Node or Group (Distant) due to either only dema…
395 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to either de…
396 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
401 …as reloaded with Modified (M) data from another core's L2 on the same chip due to either demand lo…
402 …as reloaded with Modified (M) data from another core's L2 on the same chip due to either only dema…
407 … was reloaded with Shared (S) data from another core's L2 on the same chip due to either demand lo…
408 … was reloaded with Shared (S) data from another core's L2 on the same chip due to either only dema…
413 …r's data cache was reloaded from a location other than the local core's L2 due to either demand lo…
414 …r's data cache was reloaded from a location other than the local core's L2 due to either only dema…
419 … data cache was reloaded from local core's L2 with load hit store conflict due to either demand lo…
420 … data cache was reloaded from local core's L2 with load hit store conflict due to either only dema…
425 …ssor's data cache was reloaded from local core's L2 with dispatch conflict due to either demand lo…
426 …ssor's data cache was reloaded from local core's L2 with dispatch conflict due to either only dema…
431 …reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either demand lo…
432 …reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only dema…
437 … processor's data cache was reloaded from local core's L2 without conflict due to either demand lo…
438 … processor's data cache was reloaded from local core's L2 without conflict due to either only dema…
443 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to either de…
444 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o…
449 …eloaded with Modified (M) data from another core's ECO L3 on the same chip due to either demand lo…
450 …eloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only dema…
455 … reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either demand lo…
456 … reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only dema…
461 …as reloaded with Modified (M) data from another core's L3 on the same chip due to either demand lo…
462 …as reloaded with Modified (M) data from another core's L3 on the same chip due to either only dema…
467 … was reloaded with Shared (S) data from another core's L3 on the same chip due to either demand lo…
468 … was reloaded with Shared (S) data from another core's L3 on the same chip due to either only dema…
473 …r's data cache was reloaded from a location other than the local core's L3 due to either demand lo…
474 …r's data cache was reloaded from a location other than the local core's L3 due to either only dema…
479 …ssor's data cache was reloaded from local core's L3 with dispatch conflict due to either demand lo…
480 …ssor's data cache was reloaded from local core's L3 with dispatch conflict due to either only dema…
485 …reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either demand lo…
486 …reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only dema…
491 … processor's data cache was reloaded from local core's L3 without conflict due to either demand lo…
492 … processor's data cache was reloaded from local core's L3 without conflict due to either only dema…
497 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
498 …": "The processor's data cache was reloaded from the local chip's L4 cache due to either only dema…
503 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to e…
504 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to …
509 … reloaded from a memory location including L4 from local remote or distant due to either demand lo…
510 … reloaded from a memory location including L4 from local remote or distant due to either only dema…
515 …ied data from another core's L2/L3 on a different chip (remote or distant) due to either demand lo…
516 …ied data from another core's L2/L3 on a different chip (remote or distant) due to either only dema…
521 … either shared or modified data from another core's L2/L3 on the same chip due to either demand lo…
522 … either shared or modified data from another core's L2/L3 on the same chip due to either only dema…
527 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand lo…
528 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only dema…
533 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand lo…
534 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only dema…
539 …he was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either demand lo…
540 …he was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only dema…
545 …as reloaded from another chip's memory on the same Node or Group ( Remote) due to either demand lo…
546 …as reloaded from another chip's memory on the same Node or Group ( Remote) due to either only dema…
599 … was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
600 …as reloaded with Modified (M) data from another core's L2 on the same chip due to either only dema…
605 …he was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
606 … was reloaded with Shared (S) data from another core's L2 on the same chip due to either only dema…
611 … reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load",
612 …eloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only dema…
617 …as reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load",
618 … reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only dema…
623 … was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load",
624 …as reloaded with Modified (M) data from another core's L3 on the same chip due to either only dema…
629 …he was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load",
630 … was reloaded with Shared (S) data from another core's L3 on the same chip due to either only dema…
635 …as reloaded from a memory location including L4 from local remote or distant due to a demand load",
719 "BriefDescription": "Dispatch Hold: Due to TLBIE",
725 "BriefDescription": "Dispatch held due to Issue q full",
732 "PublicDescription": "Dispatch held due to Mapper full"
737 "BriefDescription": "Dispatch held due SRQ no room",
743 "BriefDescription": "Dispatch Hold Due to no space in the GCT",
755 …nto the TLB with Modified (M) data from another core's L2 on the same chip due to a data side requ…
761 … into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side requ…
767 … was loaded into the TLB from local core's L2 with load hit store conflict due to a data side requ…
773 … Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side requ…
779 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side requ…
785 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side requ…
791 …nto the TLB with Modified (M) data from another core's L3 on the same chip due to a data side requ…
797 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side requ…
803 …"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing f…
1007 "BriefDescription": "Gct empty for this thread due to branch mispred",
1013 "BriefDescription": "Gct empty for this thread due to Icache Miss and branch mispred",
1025 …"BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to Issue q …
1031 …"BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to Mapper f…
1037 "BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to sync",
1043 …"BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to SRQ full…
1049 "BriefDescription": "Gct empty for this thread due to icache l3 miss",
1055 "BriefDescription": "Gct empty for this thread due to Icache Miss",
1151 …Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last",
1169 …"BriefDescription": "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 …
1175 "BriefDescription": "L2 I cache demand request due to branch Mispredict ( 15 cycle path)",
1193 "BriefDescription": "Prefetch Canceled due to icache hit",
1205 "BriefDescription": "Prefetch Canceled due to page boundary",
1241 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetc…
1242 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru…
1247 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetc…
1248 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru…
1253 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to instruction fetc…
1254 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instru…
1259 …as reloaded from another chip's memory on the same Node or Group (Distant) due to instruction fetc…
1260 …as reloaded from another chip's memory on the same Node or Group (Distant) due to either an instru…
1265 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to in…
1266 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e…
1271 …as reloaded with Modified (M) data from another core's L2 on the same chip due to instruction fetc…
1272 …as reloaded with Modified (M) data from another core's L2 on the same chip due to either an instru…
1277 … was reloaded with Shared (S) data from another core's L2 on the same chip due to instruction fetc…
1278 … was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instru…
1283 …truction cache was reloaded from a location other than the local core's L2 due to instruction fetc…
1284 …truction cache was reloaded from a location other than the local core's L2 due to either an instru…
1289 …ction cache was reloaded from local core's L2 with load hit store conflict due to instruction fetc…
1290 …ction cache was reloaded from local core's L2 with load hit store conflict due to either an instru…
1295 …Instruction cache was reloaded from local core's L2 with dispatch conflict due to instruction fetc…
1296 …Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instru…
1301 …eloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to instruction fetc…
1302 …eloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instru…
1307 …sor's Instruction cache was reloaded from local core's L2 without conflict due to instruction fetc…
1308 …sor's Instruction cache was reloaded from local core's L2 without conflict due to either an instru…
1313 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to in…
1314 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to e…
1319 …eloaded with Modified (M) data from another core's ECO L3 on the same chip due to instruction fetc…
1320 …eloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instru…
1325 … reloaded with Shared (S) data from another core's ECO L3 on the same chip due to instruction fetc…
1326 … reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instru…
1331 …as reloaded with Modified (M) data from another core's L3 on the same chip due to instruction fetc…
1332 …as reloaded with Modified (M) data from another core's L3 on the same chip due to either an instru…
1337 … was reloaded with Shared (S) data from another core's L3 on the same chip due to instruction fetc…
1338 … was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instru…
1343 …truction cache was reloaded from a location other than the local core's L3 due to a instruction fe…
1344 …truction cache was reloaded from a location other than the local core's L3 due to either an instru…
1349 …Instruction cache was reloaded from local core's L3 with dispatch conflict due to instruction fetc…
1350 …Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instru…
1355 …eloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to instruction fetc…
1356 …eloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instru…
1361 …sor's Instruction cache was reloaded from local core's L3 without conflict due to instruction fetc…
1362 …sor's Instruction cache was reloaded from local core's L3 without conflict due to either an instru…
1367 … processor's Instruction cache was reloaded from the local chip's L4 cache due to instruction fetc…
1368 … processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instru…
1373 …he processor's Instruction cache was reloaded from the local chip's Memory due to instruction fetc…
1374 …he processor's Instruction cache was reloaded from the local chip's Memory due to either an instru…
1379 … reloaded from a memory location including L4 from local remote or distant due to instruction fetc…
1380 … reloaded from a memory location including L4 from local remote or distant due to either an instru…
1385 …ied data from another core's L2/L3 on a different chip (remote or distant) due to instruction fetc…
1386 …ied data from another core's L2/L3 on a different chip (remote or distant) due to either an instru…
1391 … either shared or modified data from another core's L2/L3 on the same chip due to instruction fetc…
1392 … either shared or modified data from another core's L2/L3 on the same chip due to either an instru…
1397 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetc…
1398 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instru…
1403 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetc…
1404 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instru…
1409 …he was reloaded from another chip's L4 on the same Node or Group ( Remote) due to instruction fetc…
1410 …he was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instru…
1415 …as reloaded from another chip's memory on the same Node or Group ( Remote) due to instruction fetc…
1416 …as reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instru…
1475 …as reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction f…
1476 …as reloaded with Modified (M) data from another core's L2 on the same chip due to either an instru…
1481 … was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction f…
1482 … was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instru…
1487 …eloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction f…
1488 …eloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instru…
1493 … reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction f…
1494 … reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instru…
1499 …as reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction f…
1500 …as reloaded with Modified (M) data from another core's L3 on the same chip due to either an instru…
1505 … was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction f…
1506 … was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instru…
1523 …nto the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction si…
1529 … into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction si…
1535 … was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction si…
1541 … Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction si…
1547 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction si…
1553 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction si…
1559 …nto the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction si…
1565 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction si…
1625 "BriefDescription": "ISU reject due to resource not available",
1637 "BriefDescription": "ISU reject due to source not available",
1925 "BriefDescription": "LS0 Erat miss due to prefetch",
1926 "PublicDescription": "LS0 Erat miss due to prefetch42"
1943 "BriefDescription": "LS1 Erat miss due to prefetch",
1944 "PublicDescription": "LS1 Erat miss due to prefetch42"
2309 "BriefDescription": "Erat miss due to prefetch, on either pipe",
2507 … was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load",
2513 …les to reload with Modified (M) data from another core's L2 on the same chip due to a marked load",
2519 …he was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load",
2525 …ycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load",
2531 … reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
2537 …to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
2543 …as reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
2549 …s to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
2555 … was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load",
2561 …les to reload with Modified (M) data from another core's L3 on the same chip due to a marked load",
2567 …he was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load",
2573 …ycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load",
2579 …as reloaded from a memory location including L4 from local remote or distant due to a marked load",
2585 …nto the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data si…
2591 … into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data si…
2597 … was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data si…
2603 … Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data si…
2609 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data si…
2615 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data si…
2621 …nto the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data si…
2627 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data si…
2717 "BriefDescription": "LSU marked reject due to ERAT (up to 2 per cycle)",
2939 …"BriefDescription": "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to …