powerpc/power8/metrics.json

46         "MetricExpr": "(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / PM_RUN_INST_CMPL * 100",
52 …"MetricExpr": "(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / (PM_BR_PRED_LSTACK_BR0 + PM_BR_PRED_LSTACK_…
124         "MetricExpr": "(PM_CMPLU_STALL_BRU_CRU - PM_CMPLU_STALL_BRU) / PM_RUN_INST_CMPL",
135         "BriefDescription": "Cycles stalled by FXU Multi-Cycle Instructions",
148 …"MetricExpr": "(PM_CMPLU_STALL_FXU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_FXLONG / PM_RUN_INST_CMPL…
208         "MetricExpr": "(PM_GCT_NOSLOT_IC_MISS - PM_GCT_NOSLOT_IC_L3MISS) / PM_RUN_INST_CMPL",
213 …      "BriefDescription": "Cycles stalled by GCT empty due to Icache misses that resolve off-chip",
220 …L) - (PM_GCT_NOSLOT_IC_MISS  / PM_RUN_INST_CMPL) - (PM_GCT_NOSLOT_BR_MPRED / PM_RUN_INST_CMPL) - (…
237         "BriefDescription": "Cycles stalled by D-Cache Misses",
243 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in distant interventions and m…
244 …"MetricExpr": "(PM_CMPLU_STALL_DMISS_L3MISS - PM_CMPLU_STALL_DMISS_LMEM - PM_CMPLU_STALL_DMISS_L21…
249 …  "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in remote or distant caches",
255 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t…
261         "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3",
267 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t…
268 …"MetricExpr": "(PM_CMPLU_STALL_DMISS_L2L3 - PM_CMPLU_STALL_DMISS_L2L3_CONFLICT) / PM_RUN_INST_CMPL…
273 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in other core's caches or memo…
279 …  "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in local memory or local L4",
285 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in remote interventions and me…
316 …- (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_REJECT / PM_RUN_INST_CMPL) - (…
328 …REJECT / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_REJECT_LHS / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_ERAT…
373 …": "(PM_CMPLU_STALL_THRD - PM_CMPLU_STALL_LWSYNC - PM_CMPLU_STALL_HWSYNC - PM_CMPLU_STALL_MEM_ECC_…
379 …- (PM_CMPLU_STALL / PM_RUN_INST_CMPL) - (PM_GCT_NOSLOT_CYC / PM_RUN_INST_CMPL) - (PM_NTCG_ALL_FIN …
385 …- (PM_CMPLU_STALL_BRU_CRU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_FXU / PM_RUN_INST_CMPL) - (PM_CMPL…
415 …"MetricExpr": "(PM_CMPLU_STALL_VSU - PM_CMPLU_STALL_VECTOR - PM_CMPLU_STALL_SCALAR) / PM_RUN_INST_…
433 …"MetricExpr": "(PM_CMPLU_STALL_SCALAR / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_SCALAR_LONG / PM_RUN_I…
451         "MetricExpr": "(PM_CMPLU_STALL_VECTOR - PM_CMPLU_STALL_VECTOR_LONG) / PM_RUN_INST_CMPL",
492 …": "Percentage of L2 load hits per instruction where the L2 experienced a Load-Hit-Store conflict",
510 … of L2 load hits per instruction where the L2 experienced some conflict other than Load-Hit-Store",
642         "BriefDescription": "Percentage of DL1 reloads from L2 with a Load-Hit-Store conflict",
654 …riefDescription": "Percentage of DL1 reloads from L2 with some conflict other than Load-Hit-Store",
889         "MetricExpr": "PM_GCT_UTIL_11_14_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
895         "MetricExpr": "PM_GCT_UTIL_15_17_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
901         "MetricExpr": "PM_GCT_UTIL_18_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
907         "MetricExpr": "PM_GCT_UTIL_1_2_ENTRIES /  ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
913         "MetricExpr": "PM_GCT_UTIL_3_6_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
919         "MetricExpr": "PM_GCT_UTIL_7_10_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
1038         "BriefDescription": "Instruction dispatch-to-completion ratio",
1219         "MetricExpr": "(PM_L1_ICACHE_MISS - PM_IC_PREF_WRITE) / PM_L1_ICACHE_MISS",
1326 …"BriefDescription": "Average number of stores that gather in the store buffer before being sent to…
1344         "BriefDescription": "average L1 miss latency using marked events",
1350         "BriefDescription": "Average icache miss latency",
1356         "BriefDescription": "average service time for SYNC",
1362         "BriefDescription": "Cycles LMQ slot0 was active on an average",
1368 …"BriefDescription": "Average number of cycles LRQ stays active for one load.  Slot 0 is VALID ONLY…
1374 …"BriefDescription": "Average number of cycles LRQ stays active for one load.  Slot 43 is valid ONL…
1380 …"BriefDescription": "Average number of cycles SRQ stays active for one load.  Slot 0 is VALID ONLY…
1386 …"BriefDescription": "Average number of cycles SRQ stays active for one load.  Slot 39 is valid ONL…
1416         "BriefDescription": "Distant L4 average load latency",
1434 …"BriefDescription": "Average load latency for all marked demand loads that came from L2.1 in the M…
1440 …"BriefDescription": "Average load latency for all marked demand loads that came from L2.1 in the S…
1446 …ion": "Average load latency for all marked demand loads that came from the L2 and suffered a confl…
1452 …on": "Average load latency for all marked demand loads that came from the L2 and suffered a confli…
1458 …      "BriefDescription": "Average load latency for all marked demand loads that came from the L2",
1464 …"BriefDescription": "Average load latency for all marked demand loads that were satisfied by lines…
1470 …"BriefDescription": "Average load latency for all marked demand loads that came from the L2 and su…
1476 …"BriefDescription": "Average load latency for all marked demand loads that came from the L3 and be…
1494 …      "BriefDescription": "Average load latency for all marked demand loads that came from the L3",
1500 …"BriefDescription": "Average load latency for all marked demand loads that came from the L3 and su…
1506 …"BriefDescription": "Average load latency for all marked demand loads that come from beyond the L3…
1512 …"BriefDescription": "Average latency for marked reloads that hit in the L3 on the MEPF state.  i.e…
1518         "BriefDescription": "Local L4 average load latency",
1530 …tion": "Latency for marked reloads that hit in the L2 or L3 of any other core on a different chip",
1536 …ription": "Latency for marked reloads that hit in the L2 or L3 of any other core on the same chip",
1554         "BriefDescription": "Remote L4 average load latency",
1573         "MetricExpr": "PM_LSU_REJECT_ERAT_MISS * 100  / (PM_LSU_FIN - PM_LSU_FX_FIN)",
1585         "MetricExpr": "PM_LSU_REJECT_LHS *100/ (PM_LSU_FIN - PM_LSU_FX_FIN)",
1609         "MetricExpr": "PM_LSU_REJECT *100/ (PM_LSU_FIN - PM_LSU_FX_FIN)",
1926 …"BriefDescription": "Fraction of hits on any Centaur (local, remote, or distant) on either L4 or D…
1946 …   "BriefDescription": "Fraction of hits on a distant chip's Centaur (L4 or DRAM) per L1 load ref",
1971 …tion": "Fraction of hits of a line in the M (exclusive) state on the L2 or L3 of a core on a dista…
1976 …"BriefDescription": "Fraction of hits of a line in the S state on the L2 or L3 of a core on a dist…
1981         "BriefDescription": "Fraction of hits on a distant Centaur's cache per L1 load ref",
1986         "BriefDescription": "Fraction of hits on a distant Centaur's DRAM per L1 load ref",
2002         "MetricExpr": "(PM_GRP_CMPL / PM_RUN_INST_CMPL) - (PM_1PLUS_PPC_CMPL / PM_RUN_INST_CMPL)",
2037         "MetricExpr": "(PM_LD_REF_L1 - PM_LD_MISS_L1) / PM_LD_REF_L1",
2046 …      "BriefDescription": "Fraction of hits on another core's L2 on the same chip per L1 load ref",
2051 …ription": "Fraction of hits of a line in the M (exclusive) state on another core's L2 on the same …
2056 …"BriefDescription": "Fraction of hits of a line in the S state on another core's L2 on the same ch…
2061 …"BriefDescription": "Average number of Castout machines used.  1 of 16 CO machines is sampled ever…
2076 …on": "Fraction of L2 load hits per L1 load ref where the L2 experienced a Load-Hit-Store conflict",
2086 … of L2 load hits per L1 load ref where the L2 experienced some conflict other than Load-Hit-Store",
2091 …"BriefDescription": "Average number of Read/Claim machines used.  1 of 16 RC machines is sampled e…
2096 …"BriefDescription": "Average number of Snoop machines used.  1 of 8 SN machines is sampled every L…
2106 …      "BriefDescription": "Fraction of hits on another core's L3 on the same chip per L1 load ref",
2111 …ription": "Fraction of hits of a line in the M (exclusive) state on another core's L3 on the same …
2116 …"BriefDescription": "Fraction of hits of a line in the S state on another core's L3 on the same ch…
2141 …"BriefDescription": "Fraction of L3 hits on lines that were not in the MEPF state per L1 load ref",
2142         "MetricExpr": "(PM_DATA_FROM_L3 - PM_DATA_FROM_L3_MEPF) / PM_LD_REF_L1",
2146 …"BriefDescription": "Fraction of L3 hits on lines that were recently prefetched into the L3 (MEPF …
2151         "BriefDescription": "Fraction of hits on a local Centaur's cache per L1 load ref",
2156         "BriefDescription": "Fraction of hits on a local Centaur's DRAM per L1 load ref",
2161         "BriefDescription": "Fraction of hits on a local Centaur (L4 or DRAM) per L1 load ref",
2167 …cExpr": "(PM_CMPLU_STALL_LSU - PM_CMPLU_STALL_REJECT - PM_CMPLU_STALL_DCACHE_MISS - PM_CMPLU_STALL…
2171 …"BriefDescription": "Fraction of hits on another core's L2 or L3 on a different chip (remote or di…
2176 …"BriefDescription": "Fraction of hits on another core's L2 or L3 on the same chip per L1 load ref",
2181 …    "BriefDescription": "Fraction of hits on a remote chip's Centaur (L4 or DRAM) per L1 load ref",
2191 …tion": "Fraction of hits of a line in the M (exclusive) state on the L2 or L3 of a core on a remot…
2196 …"BriefDescription": "Fraction of hits of a line in the S state on the L2 or L3 of a core on a remo…
2201         "BriefDescription": "Fraction of hits on a remote Centaur's cache per L1 load ref",
2206         "BriefDescription": "Fraction of hits on a remote Centaur's DRAM per L1 load ref",
2227 …    "MetricExpr": "100 * (PM_LSU0_SRQ_STFWD + PM_LSU1_SRQ_STFWD) / (PM_LD_REF_L1 - PM_LD_MISS_L1)",