powerpc/power8/marked.json

35 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
41 …ation in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node …
47 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
53 …uration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node …
155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked …
161 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load…
167 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load…
173     "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load",
179 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
185 …"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due …
191 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch…
197 …"BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts …
203 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict…
209 …"BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a m…
251 …a cache was reloaded either shared or modified data from another core's L2/L3 on a different chip …
257 … in cycles to reload either shared or modified data from another core's L2/L3 on a different chip …
263 …a cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due…
269 … in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due…
275 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or …
281 …ation in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or …
287 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or …
293 …uration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or …
365 …y was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node …
371 …try was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node …
413 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a mark…
419 … Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data…
425 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch…
431 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa…
437 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without confl…
461 … loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip …
467 … loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due…
473 …y was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or …
479 …try was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or …
785     "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt",