powerpc/power8/frontend.json

89 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f…
90 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru…
95 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f…
96 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru…
101 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction f…
102 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instru…
107 …as reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction f…
108 …as reloaded from another chip's memory on the same Node or Group (Distant) due to either an instru…
113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e…
119 …truction cache was reloaded from a location other than the local core's L2 due to an instruction f…
120 …truction cache was reloaded from a location other than the local core's L2 due to either an instru…
125 …ction cache was reloaded from local core's L2 with load hit store conflict due to an instruction f…
126 …ction cache was reloaded from local core's L2 with load hit store conflict due to either an instru…
131 …Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction f…
132 …Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instru…
137 …eloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction f…
138 …eloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instru…
143 …sor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction f…
144 …sor's Instruction cache was reloaded from local core's L2 without conflict due to either an instru…
149 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an…
150 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to e…
161 …truction cache was reloaded from a location other than the local core's L3 due to a instruction fe…
162 …truction cache was reloaded from a location other than the local core's L3 due to either an instru…
167 …Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction f…
168 …Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instru…
173 …eloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction f…
174 …eloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instru…
179 …sor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction f…
180 …sor's Instruction cache was reloaded from local core's L3 without conflict due to either an instru…
185 … processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction f…
186 … processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instru…
191 …he processor's Instruction cache was reloaded from the local chip's Memory due to an instruction f…
192 …he processor's Instruction cache was reloaded from the local chip's Memory due to either an instru…
197 … reloaded from a memory location including L4 from local remote or distant due to an instruction f…
198 … reloaded from a memory location including L4 from local remote or distant due to either an instru…
203 …ied data from another core's L2/L3 on a different chip (remote or distant) due to an instruction f…
204 …ied data from another core's L2/L3 on a different chip (remote or distant) due to either an instru…
209 … either shared or modified data from another core's L2/L3 on the same chip due to an instruction f…
210 … either shared or modified data from another core's L2/L3 on the same chip due to either an instru…
215 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction f…
216 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instru…
221 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction f…
222 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instru…
227 …he was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction f…
228 …he was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instru…
233 …as reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction f…
234 …as reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instru…
293 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction si…
299 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction si…
305 …into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction si…
311 …nto the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction si…
317 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a inst…
323 …try was loaded into the TLB from a location other than the local core's L2 due to a instruction si…
329 …the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction si…
335 … Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction si…
341 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a inst…
347 …try was loaded into the TLB from a location other than the local core's L3 due to a instruction si…
353 … Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction si…
359 …the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction si…
365 … Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction si…
371 …"A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction si…
377 …: "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction si…
383 …o the TLB from a memory location including L4 from local remote or distant due to a instruction si…
389 …ied data from another core's L2/L3 on a different chip (remote or distant) due to a instruction si…
395 … either shared or modified data from another core's L2/L3 on the same chip due to a instruction si…
401 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction si…
407 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction si…
413 …ed into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction si…
419 …nto the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction si…