powerpc/power10/pipeline.json

5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or…
10 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch fo…
35     "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
45 …"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling…
50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
55 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a…
75 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be…
80 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be…
85 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
90 …iefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the stor…
95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t…
100     "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions."
105     "BriefDescription": "Cycles dispatch is held."
110 …"BriefDescription": "Cycles dispatch is held because of a synchronizing instruction that requires …
115 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
130 …"BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dis…
135 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not…
140 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch du…
150 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the L…
155 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handl…
160 …"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT…
165 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
170 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
175 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
205 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the V…
210 …"BriefDescription": "Cycles when dispatch was stalled for this thread due to an instruction cache …
215 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for…
220 …"BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held…
225 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be…
230 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIE instructio…
235 …Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flu…
240 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note t…
245     "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions."
250     "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions."
255     "BriefDescription": "Cycles dispatch is held for any other reason."
260 …"BriefDescription": "Cycles dispatch is held because the STF mapper/SRB was full. Includes GPR (co…
265 …"BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instr…
270 …ption": "Cycles in which the oldest instruction in the pipeline was waiting to finish in one of th…
275 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instructio…
280 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss an…
285 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch wh…
295 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cach…
300 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the no…
305 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed poi…
310 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
315 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was not allowed to com…
330 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
335 …Cycles in which the oldest instruction in the pipeline was finishing a load after its data was rel…
340 …"BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an i…
345 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be…
350 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
355     "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions."
360     "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions."
365     "BriefDescription": "Cycles dispatch is held because the XVFC mapper/SRB was full."
380 …"BriefDescription": "Cycles in which both instructions in the ICT entry pair show as finished. The…
385 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sourc…
390 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss …
395 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
400 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete becaus…
405 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
415 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction…
420 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruct…
425 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the B…
430 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting f…
435 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instructi…
440 …"BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch…
445 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any s…
450 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an n…
455 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch fo…
465 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be…
475 …"BriefDescription": "Cycles dispatch is held while waiting on the Scoreboard. This event combines …
480 …"BriefDescription": "Cycles dispatch is held because the mapper/SRB was full. Includes GPR (count,…
485     "BriefDescription": "Cycles at least one Instr Dispatched."
500 …Cycles when a TLBIE/SLBIEG/SLBIAG command was held in a hottemp condition by the NCU Master. Multi…
505 …Cycles when a TLBIE/SLBIEG/SLBIAG that targets this thread's LPAR was in flight while in a hottemp…