powerpc/power10/marked.json

5 …instruction issued. Note that stores always get issued twice, the address gets issued to the LSU a…
15 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel…
35     "BriefDescription": "The thread has dispatched a randomly sampled marked instruction."
40     "BriefDescription": "Marked Branch Taken instruction completed."
45     "BriefDescription": "Marked instruction suffered an instruction cache miss."
55     "BriefDescription": "Marked instruction RC dispatched in L2."
60 …"BriefDescription": "Cycles in which the marked instruction is the oldest in the pipeline (next-to…
65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o…
70 …"BriefDescription": "The marked instruction was a decimal floating point operation issued to the V…
75 …"BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measure…
85     "BriefDescription": "Marked Branch instruction finished."
90 …"BriefDescription": "The marked instruction was simple fixed point that was issued to the store un…
95 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel…
105 …"BriefDescription": "Marked conditional store instruction (STCX) finished. LARX and STCX are instr…
110 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at…
120 …"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When…
140     "BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
150 …"BriefDescription": "VSU marked instruction finished. Excludes simple FX instructions issued to th…
155     "BriefDescription": "Marked load instruction completed."
160 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel…
170 …"BriefDescription": "Marked conditional store instruction (STCX) failed. LARX and STCX are instruc…
175     "BriefDescription": "Marked store instruction finished."
185 …"BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill…
205     "BriefDescription": "Marked TLBIE instruction finished. Includes TLBIE and TLBIEL instructions."
210 …"BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instru…
215     "BriefDescription": "LSU marked instruction finish."
220 …Cycles spent in the core portion of a marked STCX instruction. It starts counting when the instruc…
225 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel…
235 …"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G for a marked instruction. When …
245     "BriefDescription": "The marked instruction was flushed."
250 …"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When …
255     "BriefDescription": "Marked instruction completed."
260 …"BriefDescription": "The DPTEG required for the marked load/store instruction in execution was mis…
265 …on": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a dema…
270 …s reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."