powerpc/power10/marked.json

15 …only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes …
20 …"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specif…
25 …d. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes…
50     "BriefDescription": "Marked demand reload."
95 …only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes …
100 …"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specif…
120 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes…
125 …s data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked …
130     "BriefDescription": "Marked demand data load miss counted at finish time."
135 …eloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked …
145 …d. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes…
160 …only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes …
165 …"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specif…
200 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes…
225 …only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes …
230 …"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specif…
235 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes…
240 …K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes…
250 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes…
260 …store instruction in execution was missing from the TLB. This event only counts for demand misses."
265 … instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked …
270 …ata cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked …