Lines Matching full:prefetch

55 …"BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread t…
70 …s instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload."
75 …sor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload."
90 …che was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload."
95 …che was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload."
105 … with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload."
115 …state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload."
125 …ispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload."
135 …conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload."
150 …che was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload."
155 …che was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload."
170 …s instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
175 …sor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
185 … with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload."
195 …state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload."
205 …sor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
220 …uction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload."
225 …1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload."
235 …rom another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
245 …rom another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
260 …rom another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
265 …rom another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
275 …rom another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
285 …rom another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
300 …rom another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
305 …rom another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
315 …other core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload."
325 …other core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload."
340 …other core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload."
345 …other core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload."
355 … another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
365 … another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
380 … another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
385 … another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
395 … another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
405 … another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
420 … another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
425 … another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
435 …er core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload."
445 …er core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload."
460 …er core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload."
465 …er core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload."
480 …struction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload."
485 …s L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload."
495 …a cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch reload."
505 … cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch reload."
520 …s reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
525 …s reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
535 …xclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload."
545 …xclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload."
560 …he was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload."
565 …he was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload."
575 …xclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload."
585 …xclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload."
600 …he was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload."
605 …he was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload."
615 …ve) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload."
625 …ve) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload."
640 … reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload."
645 … reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload."
660 …struction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload."
665 …s L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload."
675 …ta cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch reload."
685 …a cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch reload."
700 …as reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
705 …as reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
715 …clusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload."
725 …clusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload."
740 …e was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload."
745 …e was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload."
755 …clusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload."
765 …clusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload."
780 …e was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload."
785 …e was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload."
795 …e) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload."
805 …e) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload."
820 …reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload."
825 …reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload."
840 …truction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload."
845 … L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload."
855 …a cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch reload."
865 … cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch reload."
880 …s reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
885 …s reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
900 … reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload."
905 … reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload."
920 …loaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload."
925 …loaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload."
940 …ction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload."
945 … data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload."
960 …ion cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a mark…
965 …ata cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a mark…
980 …loaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a mark…
985 …loaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a mark…
995 … NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a mark…
1005 …out dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a mark…
1015 …nflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a mark…
1025 …ther than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a mark…
1040 …loaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a mark…
1045 …loaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a mark…
1060 …ion cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a mark…
1065 …ata cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a mark…
1075 … NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a mark…
1085 …out dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a mark…
1095 …ata cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a mark…
1110 …he was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a mark…
1115 …he was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a mark…
1125 …r core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1135 …r core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1150 …r core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1155 …r core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1165 …r core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1175 …r core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1190 …r core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1195 …r core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1205 …'s L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1215 …'s L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1230 …'s L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1235 …'s L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a mark…
1245 …ore's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1255 …ore's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1270 …ore's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1275 …ore's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1285 …ore's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1295 …ore's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1310 …ore's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1315 …ore's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1325 …L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1335 …L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1350 …L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1355 …L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a mark…
1370 …cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a mark…
1375 …cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a mark…
1385 …s reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch reload for a mark…
1395 … reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch reload for a mark…
1410 … from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a mark…
1415 … from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a mark…
1425 …state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a mark…
1435 …state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a mark…
1450 …oaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a mark…
1455 …oaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a mark…
1465 …state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a mark…
1475 …state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a mark…
1490 …oaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a mark…
1495 …oaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a mark…
1505 …from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a mark…
1515 …from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a mark…
1530 …from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a mark…
1535 …from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a mark…
1550 …cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a mark…
1555 …cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a mark…
1565 …as reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch reload for a mark…
1575 …s reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch reload for a mark…
1590 …d from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a mark…
1595 …d from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a mark…
1605 …tate from another core's L2 from a distant chip due to a demand miss or prefetch reload for a mark…
1615 …tate from another core's L2 from a distant chip due to a demand miss or prefetch reload for a mark…
1630 …aded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a mark…
1635 …aded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a mark…
1645 …tate from another core's L3 from a distant chip due to a demand miss or prefetch reload for a mark…
1655 …tate from another core's L3 from a distant chip due to a demand miss or prefetch reload for a mark…
1670 …aded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a mark…
1675 …aded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a mark…
1685 …rom another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a mark…
1695 …rom another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a mark…
1710 …rom another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a mark…
1715 …rom another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a mark…
1730 …ache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a mark…
1735 …ache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a mark…
1745 …s reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch reload for a mark…
1755 … reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch reload for a mark…
1770 … from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a mark…
1775 … from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a mark…
1790 …from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a mark…
1795 …from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a mark…
1810 …m another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a mark…
1815 …m another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a mark…
1830 …e was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a mark…
1835 …e was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a mark…