powerpc/power10/datasource.json

10 …er this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are i…
40 …"All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happ…
45 …All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happ…
50 … "All successful D-side store dispatches for this thread that were L2 hits. Since the event happen…
55 … missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 t…
120 …or's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the lo…
125 …or's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the lo…
130 …ta cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the loca…
135 …ta cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the loca…
230 …line that was not in the M (exclusive) state from another core's L2 on the same chip in the same r…
235 …line that was not in the M (exclusive) state from another core's L2 on the same chip in the same r…
240 …oaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same r…
245 …oaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same r…
250 …e processor's instruction cache was reloaded from another core's L2 on the same chip in the same r…
255 … "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same r…
260 …e processor's instruction cache was reloaded from another core's L2 on the same chip in the same r…
265 … "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same r…
270 …line that was not in the M (exclusive) state from another core's L3 on the same chip in the same r…
275 …line that was not in the M (exclusive) state from another core's L3 on the same chip in the same r…
280 …oaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same r…
285 …oaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same r…
290 …e processor's instruction cache was reloaded from another core's L3 on the same chip in the same r…
295 … "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same r…
300 …e processor's instruction cache was reloaded from another core's L3 on the same chip in the same r…
305 … "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same r…
310 …hat was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same r…
315 …hat was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same r…
320 …with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same r…
325 …with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same r…
330 …essor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same r…
335 …processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same r…
340 …essor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same r…
345 …processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same r…
350 …line that was not in the M (exclusive) state from another core's L2 on the same chip in a differen…
355 …line that was not in the M (exclusive) state from another core's L2 on the same chip in a differen…
360 …oaded with a line in the M (exclusive) state from another core's L2 on the same chip in a differen…
365 …oaded with a line in the M (exclusive) state from another core's L2 on the same chip in a differen…
370 …e processor's instruction cache was reloaded from another core's L2 on the same chip in a differen…
375 … "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a differen…
380 …e processor's instruction cache was reloaded from another core's L2 on the same chip in a differen…
385 … "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a differen…
390 …line that was not in the M (exclusive) state from another core's L3 on the same chip in a differen…
395 …line that was not in the M (exclusive) state from another core's L3 on the same chip in a differen…
400 …oaded with a line in the M (exclusive) state from another core's L3 on the same chip in a differen…
405 …oaded with a line in the M (exclusive) state from another core's L3 on the same chip in a differen…
410 …e processor's instruction cache was reloaded from another core's L3 on the same chip in a differen…
415 … "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a differen…
420 …e processor's instruction cache was reloaded from another core's L3 on the same chip in a differen…
425 … "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a differen…
430 …hat was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a differen…
435 …hat was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a differen…
440 …with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a differen…
445 …with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a differen…
450 …essor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a differen…
455 …processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a differen…
460 …essor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a differen…
465 …processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a differen…
470 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory d…
475 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due t…
480 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory d…
485 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due t…
490 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cac…
495 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cac…
500 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI mem…
505 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI mem…
510 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI…
515 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cac…
520 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI…
525 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cac…
530 …t was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand mis…
535 …t was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand mis…
540 …th a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand mis…
545 …th a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand mis…
550 …sor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand mis…
555 …ocessor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand mis…
560 …sor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand mis…
565 …ocessor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand mis…
570 …t was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand mis…
575 …t was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand mis…
580 …th a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand mis…
585 …th a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand mis…
590 …sor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand mis…
595 …ocessor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand mis…
600 …sor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand mis…
605 …ocessor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand mis…
610 …not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand mis…
615 …not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand mis…
620 …ine in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand mis…
625 …ine in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand mis…
630 …instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand mis…
635 …r's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand mis…
640 …instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand mis…
645 …r's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand mis…
670 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cach…
675 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cach…
680 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memo…
685 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memo…
690 …"BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI …
695 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cach…
700 …"BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI …
705 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cach…
710 … was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand mis…
715 … was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand mis…
720 …h a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand mis…
725 …h a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand mis…
730 …or's instruction cache was reloaded from another core's L2 from a distant chip due to a demand mis…
735 …cessor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand mis…
740 …or's instruction cache was reloaded from another core's L2 from a distant chip due to a demand mis…
745 …cessor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand mis…
750 … was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand mis…
755 … was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand mis…
760 …h a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand mis…
765 …h a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand mis…
770 …or's instruction cache was reloaded from another core's L3 from a distant chip due to a demand mis…
775 …cessor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand mis…
780 …or's instruction cache was reloaded from another core's L3 from a distant chip due to a demand mis…
785 …cessor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand mis…
790 …ot in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand mis…
795 …ot in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand mis…
800 …ne in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand mis…
805 …ne in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand mis…
810 …nstruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand mis…
815 …'s L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand mis…
820 …nstruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand mis…
825 …'s L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand mis…
850 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cac…
855 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cac…
860 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI mem…
865 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI mem…
870 …"BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI…
875 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cac…
880 …"BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI…
885 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cac…
890 …instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand mis…
895 …r's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand mis…
900 …instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand mis…
905 …r's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand mis…
910 …truction cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
915 … L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
920 …truction cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
925 … L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
930 …"BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slo…
935 …"BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) d…
940 …"BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slo…
945 …"BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) d…
1010 …or's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the lo…
1015 …or's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the lo…
1020 …ta cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the loca…
1025 …ta cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the loca…
1120 …line that was not in the M (exclusive) state from another core's L2 on the same chip in the same r…
1125 …line that was not in the M (exclusive) state from another core's L2 on the same chip in the same r…
1130 …oaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same r…
1135 …oaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same r…
1140 …e processor's instruction cache was reloaded from another core's L2 on the same chip in the same r…
1145 … "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same r…
1150 …e processor's instruction cache was reloaded from another core's L2 on the same chip in the same r…
1155 … "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same r…
1160 …line that was not in the M (exclusive) state from another core's L3 on the same chip in the same r…
1165 …line that was not in the M (exclusive) state from another core's L3 on the same chip in the same r…
1170 …oaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same r…
1175 …oaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same r…
1180 …e processor's instruction cache was reloaded from another core's L3 on the same chip in the same r…
1185 … "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same r…
1190 …e processor's instruction cache was reloaded from another core's L3 on the same chip in the same r…
1195 … "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same r…
1200 …hat was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same r…
1205 …hat was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same r…
1210 …with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same r…
1215 …with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same r…
1220 …essor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same r…
1225 …processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same r…
1230 …essor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same r…
1235 …processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same r…
1240 …line that was not in the M (exclusive) state from another core's L2 on the same chip in a differen…
1245 …line that was not in the M (exclusive) state from another core's L2 on the same chip in a differen…
1250 …oaded with a line in the M (exclusive) state from another core's L2 on the same chip in a differen…
1255 …oaded with a line in the M (exclusive) state from another core's L2 on the same chip in a differen…
1260 …e processor's instruction cache was reloaded from another core's L2 on the same chip in a differen…
1265 … "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a differen…
1270 …e processor's instruction cache was reloaded from another core's L2 on the same chip in a differen…
1275 … "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a differen…
1280 …line that was not in the M (exclusive) state from another core's L3 on the same chip in a differen…
1285 …line that was not in the M (exclusive) state from another core's L3 on the same chip in a differen…
1290 …oaded with a line in the M (exclusive) state from another core's L3 on the same chip in a differen…
1295 …oaded with a line in the M (exclusive) state from another core's L3 on the same chip in a differen…
1300 …e processor's instruction cache was reloaded from another core's L3 on the same chip in a differen…
1305 … "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a differen…
1310 …e processor's instruction cache was reloaded from another core's L3 on the same chip in a differen…
1315 … "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a differen…
1320 …hat was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a differen…
1325 …hat was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a differen…
1330 …with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a differen…
1335 …with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a differen…
1340 …essor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a differen…
1345 …processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a differen…
1350 …essor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a differen…
1355 …processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a differen…
1360 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory d…
1365 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due t…
1370 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory d…
1375 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due t…
1380 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cac…
1385 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cac…
1390 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI mem…
1395 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI mem…
1400 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI…
1405 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cac…
1410 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI…
1415 …"BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cac…
1420 …t was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand mis…
1425 …t was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand mis…
1430 …th a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand mis…
1435 …th a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand mis…
1440 …sor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand mis…
1445 …ocessor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand mis…
1450 …sor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand mis…
1455 …ocessor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand mis…
1460 …t was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand mis…
1465 …t was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand mis…
1470 …th a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand mis…
1475 …th a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand mis…
1480 …sor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand mis…
1485 …ocessor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand mis…
1490 …sor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand mis…
1495 …ocessor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand mis…
1500 …not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand mis…
1505 …not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand mis…
1510 …ine in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand mis…
1515 …ine in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand mis…
1520 …instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand mis…
1525 …r's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand mis…
1530 …instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand mis…
1535 …r's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand mis…
1560 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cach…
1565 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cach…
1570 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memo…
1575 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memo…
1580 …"BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI …
1585 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cach…
1590 …"BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI …
1595 …"BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cach…
1600 … was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand mis…
1605 … was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand mis…
1610 …h a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand mis…
1615 …h a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand mis…
1620 …or's instruction cache was reloaded from another core's L2 from a distant chip due to a demand mis…
1625 …cessor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand mis…
1630 …or's instruction cache was reloaded from another core's L2 from a distant chip due to a demand mis…
1635 …cessor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand mis…
1640 … was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand mis…
1645 … was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand mis…
1650 …h a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand mis…
1655 …h a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand mis…
1660 …or's instruction cache was reloaded from another core's L3 from a distant chip due to a demand mis…
1665 …cessor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand mis…
1670 …or's instruction cache was reloaded from another core's L3 from a distant chip due to a demand mis…
1675 …cessor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand mis…
1680 …ot in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand mis…
1685 …ot in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand mis…
1690 …ne in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand mis…
1695 …ne in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand mis…
1700 …nstruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand mis…
1705 …'s L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand mis…
1710 …nstruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand mis…
1715 …'s L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand mis…
1740 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cac…
1745 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cac…
1750 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI mem…
1755 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI mem…
1760 …"BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI…
1765 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cac…
1770 …"BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI…
1775 …"BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cac…
1780 …instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand mis…
1785 …r's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand mis…
1790 …instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand mis…
1795 …r's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand mis…
1800 …truction cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
1805 … L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
1810 …truction cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
1815 … L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
1820 …"BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slo…
1825 …"BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) d…
1830 …"BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slo…
1835 …"BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) d…