Lines Matching full:instruction

35 …"BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions.…
55 …"BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread t…
60 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
70 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
80 …"BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local…
90 …"BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local…
140 …"BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local…
150 …"BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local…
160 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due t…
170 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due t…
210 …"BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L…
220 …"BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L…
250 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
260 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
290 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the …
300 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the …
330 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
340 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
370 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
380 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
410 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the …
420 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the …
450 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
460 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
470 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory d…
480 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory d…
510 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI…
520 …"BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI…
550 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
560 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
590 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a …
600 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a …
630 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
640 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
650 …"BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) d…
660 …"BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) d…
690 …"BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI …
700 …"BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI …
730 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
740 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
770 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a …
780 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a …
810 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
820 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
830 …"BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) …
840 …"BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) …
870 …"BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI…
880 …"BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI…
890 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
900 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
910 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
920 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
930 …"BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slo…
940 …"BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slo…
950 …iption": "The processor's instruction cache was reloaded from the local core's L2 due to a demand …
955 …L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction."
960 …The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or pr…
965 …eloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
970 … "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a…
975 …s reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction."
980 …essor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand mi…
985 …ource beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction."
990 …data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction."
995 …F state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1000 …without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction."
1005 …nflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1010 …h conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction."
1015 …t-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1020 …ct other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction."
1025 …t-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1030 … "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a…
1035 …s reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."
1040 …essor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand mi…
1045 …ource beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1050 …iption": "The processor's instruction cache was reloaded from the local core's L3 due to a demand …
1055 …L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction."
1060 …The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or pr…
1065 …eloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1070 …data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction."
1075 …F state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1080 …without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction."
1085 …nflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1090 …L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction."
1095 …eloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1100 …on": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a dema…
1105 … cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
1110 … processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss o…
1115 … from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1120 …other core's L2 on the same chip in the same regent due to a demand miss for a marked instruction."
1125 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1130 …other core's L2 on the same chip in the same regent due to a demand miss for a marked instruction."
1135 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1140 …cessor's instruction cache was reloaded from another core's L2 on the same chip in the same regent…
1145 …other core's L2 on the same chip in the same regent due to a demand miss for a marked instruction."
1150 …instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a…
1155 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1160 …other core's L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1165 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1170 …other core's L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1175 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1180 …cessor's instruction cache was reloaded from another core's L3 on the same chip in the same regent…
1185 …other core's L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1190 …instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a…
1195 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1200 …core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1205 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1210 …core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1215 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1220 …sor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same reg…
1225 …core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1230 …instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent du…
1235 …the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1240 …er core's L2 on the same chip in a different regent due to a demand miss for a marked instruction."
1245 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1250 …er core's L2 on the same chip in a different regent due to a demand miss for a marked instruction."
1255 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1260 …ssor's instruction cache was reloaded from another core's L2 on the same chip in a different regen…
1265 …er core's L2 on the same chip in a different regent due to a demand miss for a marked instruction."
1270 …instruction cache was reloaded from another core's L2 on the same chip in a different regent due t…
1275 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1280 …er core's L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1285 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1290 …er core's L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1295 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1300 …ssor's instruction cache was reloaded from another core's L3 on the same chip in a different regen…
1305 …er core's L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1310 …instruction cache was reloaded from another core's L3 on the same chip in a different regent due t…
1315 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1320 …e's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1325 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1330 …e's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1335 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1340 …r's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different re…
1345 …e's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1350 …instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent…
1355 … same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1360 …tion": "The processor's instruction cache was reloaded from the local chip's memory due to a deman…
1365 …ata cache was reloaded from the local chip's memory due to a demand miss for a marked instruction."
1370 …e processor's instruction cache was reloaded from the local chip's memory due to a demand miss or …
1375 …ded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction."
1380 …e was reloaded from the local chip's OpenCAPI cache due to a demand miss for a marked instruction."
1385 … the local chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction."
1390 … was reloaded from the local chip's OpenCAPI memory due to a demand miss for a marked instruction."
1395 …the local chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction."
1400 …he processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due t…
1405 …aded from the local chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1410 …or's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand…
1415 … chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1420 …ve) state from another core's L2 from a remote chip due to a demand miss for a marked instruction."
1425 …her core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1430 …ve) state from another core's L2 from a remote chip due to a demand miss for a marked instruction."
1435 …her core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1440 …"The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a…
1445 … reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction."
1450 …essor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand m…
1455 …her core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1460 …ve) state from another core's L3 from a remote chip due to a demand miss for a marked instruction."
1465 …her core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1470 …ve) state from another core's L3 from a remote chip due to a demand miss for a marked instruction."
1475 …her core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1480 …"The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a…
1485 … reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction."
1490 …essor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand m…
1495 …her core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1500 …ate from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction."
1505 …re's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1510 …ate from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction."
1515 …re's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1520 …e processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due t…
1525 …ded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction."
1530 …or's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a deman…
1535 …re's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1540 …tion": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a deman…
1545 …ata cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction."
1550 …e processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or …
1555 …ded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."
1560 …he was reloaded from a remote chip's OpenCAPI cache due to a demand miss for a marked instruction."
1565 …m a remote chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction."
1570 …e was reloaded from a remote chip's OpenCAPI memory due to a demand miss for a marked instruction."
1575 … a remote chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction."
1580 …he processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to…
1585 …oaded from a remote chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1590 …sor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand…
1595 … chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1600 …e) state from another core's L2 from a distant chip due to a demand miss for a marked instruction."
1605 …er core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1610 …e) state from another core's L2 from a distant chip due to a demand miss for a marked instruction."
1615 …er core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1620 …"The processor's instruction cache was reloaded from another core's L2 from a distant chip due to …
1625 …reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction."
1630 …ssor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand m…
1635 …er core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1640 …e) state from another core's L3 from a distant chip due to a demand miss for a marked instruction."
1645 …er core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1650 …e) state from another core's L3 from a distant chip due to a demand miss for a marked instruction."
1655 …er core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1660 …"The processor's instruction cache was reloaded from another core's L3 from a distant chip due to …
1665 …reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction."
1670 …ssor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand m…
1675 …er core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1680 …te from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction."
1685 …e's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1690 …te from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction."
1695 …e's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1700 …e processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due …
1705 …ed from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction."
1710 …r's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a deman…
1715 …e's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1720 …ion": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a deman…
1725 …ta cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction."
1730 …e processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or…
1735 …ed from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."
1740 …e was reloaded from a distant chip's OpenCAPI cache due to a demand miss for a marked instruction."
1745 … a distant chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction."
1750 … was reloaded from a distant chip's OpenCAPI memory due to a demand miss for a marked instruction."
1755 …a distant chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction."
1760 …he processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due t…
1765 …aded from a distant chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1770 …or's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand…
1775 … chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1780 …e processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due t…
1785 …ded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction."
1790 …or's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a deman…
1795 …re's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction."
1800 … processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due…
1805 … from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction."
1810 …'s instruction cache was reloaded from another core's L2 or L3 from a different chip due to a dema…
1815 …s L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction."
1820 …on": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a dem…
1825 …cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction."
1830 …processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss o…
1835 …from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."