powerpc/power10/datasource.json

15 …cessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss."
20 … "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."
30 …he processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
55 …"BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread t…
60 …n": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss."
65 …ption": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss."
70 …essor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch r…
75 …processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch r…
80 …or's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss."
85 …cessor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss."
90 …ion cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch r…
95 …ata cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch r…
100 … dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss."
105 …flicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch r…
110 …h data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss."
115 … MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch r…
120 …h data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss."
125 …ad a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch r…
130 …hat had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss."
135 …patch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch r…
140 …or's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss."
145 …cessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss."
150 …ion cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch r…
155 …ata cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch r…
160 …n": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss."
165 …ption": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss."
170 …essor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch r…
175 …processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch r…
180 … dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss."
185 …flicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch r…
190 …h data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss."
195 … MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch r…
200 …ption": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss."
205 …processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch r…
210 …e processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss."
215 … "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."
220 … instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch r…
225 …or's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch r…
230 …(exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss."
235 …tate from another core's L2 on the same chip in the same regent due to a demand miss or prefetch r…
240 …(exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss."
245 …tate from another core's L2 on the same chip in the same regent due to a demand miss or prefetch r…
250 …ache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss."
255 …ache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss."
260 …aded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch r…
265 …aded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch r…
270 …(exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss."
275 …tate from another core's L3 on the same chip in the same regent due to a demand miss or prefetch r…
280 …(exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss."
285 …tate from another core's L3 on the same chip in the same regent due to a demand miss or prefetch r…
290 …ache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss."
295 …ache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss."
300 …aded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch r…
305 …aded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch r…
310 …sive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
315 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch r…
320 …sive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
325 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch r…
330 …as reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
335 …as reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
340 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch r…
345 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch r…
350 …clusive) state from another core's L2 on the same chip in a different regent due to a demand miss."
355 …e from another core's L2 on the same chip in a different regent due to a demand miss or prefetch r…
360 …clusive) state from another core's L2 on the same chip in a different regent due to a demand miss."
365 …e from another core's L2 on the same chip in a different regent due to a demand miss or prefetch r…
370 …e was reloaded from another core's L2 on the same chip in a different regent due to a demand miss."
375 …e was reloaded from another core's L2 on the same chip in a different regent due to a demand miss."
380 …d from another core's L2 on the same chip in a different regent due to a demand miss or prefetch r…
385 …d from another core's L2 on the same chip in a different regent due to a demand miss or prefetch r…
390 …clusive) state from another core's L3 on the same chip in a different regent due to a demand miss."
395 …e from another core's L3 on the same chip in a different regent due to a demand miss or prefetch r…
400 …clusive) state from another core's L3 on the same chip in a different regent due to a demand miss."
405 …e from another core's L3 on the same chip in a different regent due to a demand miss or prefetch r…
410 …e was reloaded from another core's L3 on the same chip in a different regent due to a demand miss."
415 …e was reloaded from another core's L3 on the same chip in a different regent due to a demand miss."
420 …d from another core's L3 on the same chip in a different regent due to a demand miss or prefetch r…
425 …d from another core's L3 on the same chip in a different regent due to a demand miss or prefetch r…
430 …e) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
435 … another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch r…
440 …e) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
445 … another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch r…
450 …reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
455 …reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
460 … another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch r…
465 … another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch r…
470 …"The processor's instruction cache was reloaded from the local chip's memory due to a demand miss."
475 …n": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss."
480 …r's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch r…
485 …essor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch r…
490 … processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss."
495 …L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch r…
500 …processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss."
505 …1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch r…
510 …nstruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss."
515 …'s L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss."
520 …che was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
525 …che was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
530 …was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss."
535 …e M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch r…
540 … a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss."
545 …e M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch r…
550 …r's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss."
555 …essor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss."
560 …on cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch r…
565 …ta cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch r…
570 …was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss."
575 …e M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch r…
580 … a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss."
585 …e M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch r…
590 …r's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss."
595 …essor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss."
600 …on cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch r…
605 …ta cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch r…
610 …t in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss."
615 …xclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch r…
620 …e in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss."
625 …xclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch r…
630 …struction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss."
635 …s L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss."
640 …he was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch r…
645 …he was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch r…
650 …"The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss."
655 …n": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss."
660 …r's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch r…
665 …essor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch r…
670 …e processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss."
675 … L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch r…
680 … processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss."
685 …L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch r…
690 …instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss."
695 …r's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss."
700 …ache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
705 …ache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
710 …as not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss."
715 … M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch r…
720 …a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss."
725 … M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch r…
730 …'s instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss."
735 …ssor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss."
740 …n cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch r…
745 …a cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch r…
750 …as not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss."
755 … M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch r…
760 …a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss."
765 … M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch r…
770 …'s instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss."
775 …ssor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss."
780 …n cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch r…
785 …a cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch r…
790 … in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss."
795 …clusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch r…
800 … in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss."
805 …clusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch r…
810 …truction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss."
815 … L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss."
820 …e was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch r…
825 …e was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch r…
830 …The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss."
835 …": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss."
840 …'s instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch r…
845 …ssor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch r…
850 … processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss."
855 …L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch r…
860 …processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss."
865 …1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch r…
870 …nstruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss."
875 …'s L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss."
880 …che was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
885 …che was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
890 …struction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss."
895 …s L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss."
900 …he was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch r…
905 …he was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch r…
910 …uction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss."
915 …1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss."
920 …was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch r…
925 …was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch r…
930 … processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss."
935 …"The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss."
940 …instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch r…
945 …r's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch r…
950 …essor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked …
955 …processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked …
960 …essor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch r…
965 …processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch r…
970 …ion cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked …
975 …ata cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked …
980 …ion cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch r…
985 …ata cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch r…
990 …flicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked …
995 …flicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch r…
1000 … MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked …
1005 … MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch r…
1010 …ad a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked …
1015 …ad a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch r…
1020 …patch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked …
1025 …patch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch r…
1030 …ion cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked …
1035 …ata cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked …
1040 …ion cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch r…
1045 …ata cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch r…
1050 …essor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked …
1055 …processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked …
1060 …essor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch r…
1065 …processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch r…
1070 …flicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked …
1075 …flicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch r…
1080 … MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked …
1085 … MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch r…
1090 …processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked …
1095 …processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch r…
1100 … instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked …
1105 …or's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked …
1110 … instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch r…
1115 …or's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch r…
1120 …tate from another core's L2 on the same chip in the same regent due to a demand miss for a marked …
1125 …tate from another core's L2 on the same chip in the same regent due to a demand miss or prefetch r…
1130 …tate from another core's L2 on the same chip in the same regent due to a demand miss for a marked …
1135 …tate from another core's L2 on the same chip in the same regent due to a demand miss or prefetch r…
1140 …aded from another core's L2 on the same chip in the same regent due to a demand miss for a marked …
1145 …aded from another core's L2 on the same chip in the same regent due to a demand miss for a marked …
1150 …aded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch r…
1155 …aded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch r…
1160 …tate from another core's L3 on the same chip in the same regent due to a demand miss for a marked …
1165 …tate from another core's L3 on the same chip in the same regent due to a demand miss or prefetch r…
1170 …tate from another core's L3 on the same chip in the same regent due to a demand miss for a marked …
1175 …tate from another core's L3 on the same chip in the same regent due to a demand miss or prefetch r…
1180 …aded from another core's L3 on the same chip in the same regent due to a demand miss for a marked …
1185 …aded from another core's L3 on the same chip in the same regent due to a demand miss for a marked …
1190 …aded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch r…
1195 …aded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch r…
1200 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked …
1205 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch r…
1210 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked …
1215 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch r…
1220 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked …
1225 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked …
1230 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch r…
1235 …rom another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch r…
1240 …e from another core's L2 on the same chip in a different regent due to a demand miss for a marked …
1245 …e from another core's L2 on the same chip in a different regent due to a demand miss or prefetch r…
1250 …e from another core's L2 on the same chip in a different regent due to a demand miss for a marked …
1255 …e from another core's L2 on the same chip in a different regent due to a demand miss or prefetch r…
1260 …d from another core's L2 on the same chip in a different regent due to a demand miss for a marked …
1265 …d from another core's L2 on the same chip in a different regent due to a demand miss for a marked …
1270 …d from another core's L2 on the same chip in a different regent due to a demand miss or prefetch r…
1275 …d from another core's L2 on the same chip in a different regent due to a demand miss or prefetch r…
1280 …e from another core's L3 on the same chip in a different regent due to a demand miss for a marked …
1285 …e from another core's L3 on the same chip in a different regent due to a demand miss or prefetch r…
1290 …e from another core's L3 on the same chip in a different regent due to a demand miss for a marked …
1295 …e from another core's L3 on the same chip in a different regent due to a demand miss or prefetch r…
1300 …d from another core's L3 on the same chip in a different regent due to a demand miss for a marked …
1305 …d from another core's L3 on the same chip in a different regent due to a demand miss for a marked …
1310 …d from another core's L3 on the same chip in a different regent due to a demand miss or prefetch r…
1315 …d from another core's L3 on the same chip in a different regent due to a demand miss or prefetch r…
1320 … another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked …
1325 … another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch r…
1330 … another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked …
1335 … another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch r…
1340 … another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked …
1345 … another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked …
1350 … another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch r…
1355 … another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch r…
1360 …r's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked …
1365 …essor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked …
1370 …r's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch r…
1375 …essor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch r…
1380 …L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss for a marked …
1385 …L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch r…
1390 …1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss for a marked …
1395 …1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch r…
1400 …che was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss for a marked …
1405 …che was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss for a marked …
1410 …che was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
1415 …che was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
1420 …e M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked …
1425 …e M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch r…
1430 …e M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked …
1435 …e M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch r…
1440 …on cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked …
1445 …ta cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked …
1450 …on cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch r…
1455 …ta cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch r…
1460 …e M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked …
1465 …e M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch r…
1470 …e M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked …
1475 …e M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch r…
1480 …on cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked …
1485 …ta cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked …
1490 …on cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch r…
1495 …ta cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch r…
1500 …xclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked …
1505 …xclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch r…
1510 …xclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked …
1515 …xclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch r…
1520 …he was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked …
1525 …he was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked …
1530 …he was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch r…
1535 …he was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch r…
1540 …r's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked …
1545 …essor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked …
1550 …r's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch r…
1555 …essor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch r…
1560 … L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss for a marked …
1565 … L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch r…
1570 …L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss for a marked …
1575 …L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch r…
1580 …ache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss for a marked …
1585 …ache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss for a marked …
1590 …ache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
1595 …ache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
1600 … M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked …
1605 … M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch r…
1610 … M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked …
1615 … M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch r…
1620 …n cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked …
1625 …a cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked …
1630 …n cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch r…
1635 …a cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch r…
1640 … M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked …
1645 … M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch r…
1650 … M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked …
1655 … M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch r…
1660 …n cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked …
1665 …a cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked …
1670 …n cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch r…
1675 …a cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch r…
1680 …clusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked …
1685 …clusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch r…
1690 …clusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked …
1695 …clusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch r…
1700 …e was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked …
1705 …e was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked …
1710 …e was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch r…
1715 …e was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch r…
1720 …'s instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked …
1725 …ssor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked …
1730 …'s instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch r…
1735 …ssor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch r…
1740 …L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss for a marked …
1745 …L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch r…
1750 …1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss for a marked …
1755 …1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch r…
1760 …che was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss for a marked …
1765 …che was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss for a marked …
1770 …che was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
1775 …che was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch r…
1780 …he was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked …
1785 …he was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked …
1790 …he was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch r…
1795 …he was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch r…
1800 …was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked …
1805 …was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked …
1810 …was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch r…
1815 …was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch r…
1820 …instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked …
1825 …r's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked …
1830 …instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch r…
1835 …r's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch r…