powerpc/power10/datasource.json

30 …"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory…
70 …s instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload."
75 …sor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload."
90 …che was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload."
95 …che was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload."
105 … with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload."
115 …state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload."
125 …ispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload."
135 …conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload."
150 …che was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload."
155 …che was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload."
170 …s instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
175 …sor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
185 … with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload."
195 …state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload."
205 …sor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
220 …uction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload."
225 …1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload."
235 …rom another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
245 …rom another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
260 …rom another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
265 …rom another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
275 …rom another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
285 …rom another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
300 …rom another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
305 …rom another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
310 … valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip …
315 … M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a dem…
320 …was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip …
325 … M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a dem…
330 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
335 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
340 …n cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a dem…
345 …a cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a dem…
355 … another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
365 … another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
380 … another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
385 … another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
395 … another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
405 … another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
420 … another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
425 … another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
430 … valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip …
435 … (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a de…
440 …was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip …
445 … (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a de…
450 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
455 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
460 …cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a de…
465 …cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a de…
480 …struction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload."
485 …s L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload."
495 …a cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch reload."
505 … cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch reload."
510 …ssor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a dema…
515 …rocessor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a dema…
520 …ion cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or pref…
525 …ata cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or pref…
535 …xclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload."
545 …xclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload."
560 …he was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload."
565 …he was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload."
575 …xclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload."
585 …xclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload."
600 …he was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload."
605 …he was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload."
610 … valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chi…
615 …t in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss …
620 …was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chi…
625 …e in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss …
630 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
635 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
640 …struction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss …
645 …s L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss …
660 …struction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload."
665 …s L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload."
675 …ta cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch reload."
685 …a cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch reload."
690 …essor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a dema…
695 …processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a dema…
700 …tion cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or pref…
705 …data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or pref…
715 …clusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload."
725 …clusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload."
740 …e was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload."
745 …e was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload."
755 …clusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload."
765 …clusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload."
780 …e was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload."
785 …e was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload."
790 … valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant ch…
795 …t in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss…
800 …was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant ch…
805 …e in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss…
810 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
815 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
820 …struction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss…
825 …s L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss…
840 …truction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload."
845 … L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload."
855 …a cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch reload."
865 … cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch reload."
870 …ssor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a dema…
875 …rocessor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a dema…
880 …ion cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or pref…
885 …ata cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or pref…
890 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
895 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
900 …struction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss …
905 …s L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss …
910 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
915 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
920 …truction cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
925 … L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
940 …ction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload."
945 … data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload."
960 …struction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for …
965 …s L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for …
980 …was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for …
985 …was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for …
995 …h data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for …
1005 …e without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for …
1015 …tch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for …
1025 …lict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for …
1040 …was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for …
1045 …was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for …
1060 …struction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for …
1065 …s L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for …
1075 …h data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for …
1085 …e without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for …
1095 …s L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for …
1110 …on cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for …
1115 …ta cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for …
1125 …another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for …
1135 …another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for …
1150 …another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for …
1155 …another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for …
1165 …another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for …
1175 …another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for …
1190 …another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for …
1195 …another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for …
1200 … valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip …
1205 … M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a dem…
1210 …was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip …
1215 … M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a dem…
1220 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
1225 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
1230 …n cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a dem…
1235 …a cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a dem…
1245 …ther core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for …
1255 …ther core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for …
1270 …ther core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for …
1275 …ther core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for …
1285 …ther core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for …
1295 …ther core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for …
1310 …ther core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for …
1315 …ther core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for …
1320 … valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip …
1325 … (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a de…
1330 …was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip …
1335 … (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a de…
1340 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
1345 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
1350 …cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a de…
1355 …cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a de…
1370 …ction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for …
1375 … data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for …
1385 …che was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch reload for …
1395 …he was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch reload for …
1400 …ssor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a dema…
1405 …rocessor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a dema…
1410 …ion cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or pref…
1415 …ata cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or pref…
1425 …sive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for …
1435 …sive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for …
1450 …as reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for …
1455 …as reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for …
1465 …sive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for …
1475 …sive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for …
1490 …as reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for …
1495 …as reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for …
1500 … valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chi…
1505 …t in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss …
1510 …was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chi…
1515 …e in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss …
1520 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1525 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1530 …struction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss …
1535 …s L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss …
1550 …ction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for …
1555 … data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for …
1565 …ache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch reload for …
1575 …che was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch reload for …
1580 …essor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a dema…
1585 …processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a dema…
1590 …tion cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or pref…
1595 …data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or pref…
1605 …ive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for …
1615 …ive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for …
1630 …s reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for …
1635 …s reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for …
1645 …ive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for …
1655 …ive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for …
1670 …s reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for …
1675 …s reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for …
1680 … valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant ch…
1685 …t in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss…
1690 …was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant ch…
1695 …e in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss…
1700 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1705 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1710 …struction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss…
1715 …s L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss…
1730 …tion cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for …
1735 …data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for …
1745 …che was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch reload for …
1755 …he was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch reload for …
1760 …ssor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a dema…
1765 …rocessor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a dema…
1770 …ion cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or pref…
1775 …ata cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or pref…
1780 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1785 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1790 …struction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss …
1795 …s L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss …
1800 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1805 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1810 …truction cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
1815 … L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand mis…
1830 …n cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for …
1835 …a cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for …