powerpc/power10/datasource.json

15 …cessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss."
20 … "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."
30 …he processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
60 …n": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss."
65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
70 …: "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or…
75 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
80 …or's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss."
85 …cessor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss."
90 …'s instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or…
95 …ssor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or…
100 … dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss."
105 …ispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or…
110 …h data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss."
115 …data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or…
120 …h data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss."
125 …data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or…
130 …hat had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss."
135 …t had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or…
140 …or's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss."
145 …cessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss."
150 …'s instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or…
155 …ssor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or…
160 …n": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss."
165 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a …
170 …: "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or…
175 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a …
180 … dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss."
185 …ispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or…
190 …h data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss."
195 …data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or…
200 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a …
205 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a …
210 …e processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss."
215 … "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."
220 …processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or…
225 …The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or…
230 …(exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss."
235 …xclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or…
240 …(exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss."
245 …xclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or…
250 …ache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss."
255 …ache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss."
260 …he was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or…
265 …he was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or…
270 …(exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss."
275 …xclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or…
280 …(exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss."
285 …xclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or…
290 …ache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss."
295 …ache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss."
300 …he was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or…
305 …he was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or…
310 …sive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
315 …ve) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or…
320 …sive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
325 …ve) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or…
330 …as reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
335 …as reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
340 … reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or…
345 … reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or…
350 …clusive) state from another core's L2 on the same chip in a different regent due to a demand miss."
355 …usive) state from another core's L2 on the same chip in a different regent due to a demand miss or…
360 …clusive) state from another core's L2 on the same chip in a different regent due to a demand miss."
365 …usive) state from another core's L2 on the same chip in a different regent due to a demand miss or…
370 …e was reloaded from another core's L2 on the same chip in a different regent due to a demand miss."
375 …e was reloaded from another core's L2 on the same chip in a different regent due to a demand miss."
380 …was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or…
385 …was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or…
390 …clusive) state from another core's L3 on the same chip in a different regent due to a demand miss."
395 …usive) state from another core's L3 on the same chip in a different regent due to a demand miss or…
400 …clusive) state from another core's L3 on the same chip in a different regent due to a demand miss."
405 …usive) state from another core's L3 on the same chip in a different regent due to a demand miss or…
410 …e was reloaded from another core's L3 on the same chip in a different regent due to a demand miss."
415 …e was reloaded from another core's L3 on the same chip in a different regent due to a demand miss."
420 …was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or…
425 …was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or…
430 …e) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
435 … state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or…
440 …e) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
445 … state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or…
450 …reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
455 …reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
460 …loaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or…
465 …loaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or…
470 …"The processor's instruction cache was reloaded from the local chip's memory due to a demand miss."
475 …n": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss."
480 …he processor's instruction cache was reloaded from the local chip's memory due to a demand miss or…
485 …: "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or…
490 … processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss."
495 …rocessor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or…
500 …processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss."
505 …ocessor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or…
510 …nstruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss."
515 …'s L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss."
520 …truction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or…
525 … L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or…
530 …was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss."
535 …s not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or…
540 … a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss."
545 … line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or…
550 …r's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss."
555 …essor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss."
560 …s instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or…
565 …sor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or…
570 …was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss."
575 …s not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or…
580 … a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss."
585 … line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or…
590 …r's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss."
595 …essor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss."
600 …s instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or…
605 …sor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or…
610 …t in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss."
615 …in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or…
620 …e in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss."
625 …in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or…
630 …struction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss."
635 …s L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss."
640 …ruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or…
645 …L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or…
650 …"The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss."
655 …n": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss."
660 …he processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or…
665 …: "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or…
670 …e processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss."
675 …processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or…
680 … processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss."
685 …rocessor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or…
690 …instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss."
695 …r's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss."
700 …struction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or…
705 …s L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or…
710 …as not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss."
715 … not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or…
720 …a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss."
725 …line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or…
730 …'s instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss."
735 …ssor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss."
740 … instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or…
745 …or's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or…
750 …as not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss."
755 … not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or…
760 …a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss."
765 …line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or…
770 …'s instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss."
775 …ssor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss."
780 … instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or…
785 …or's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or…
790 … in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss."
795 …n the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or…
800 … in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss."
805 …n the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or…
810 …truction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss."
815 … L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss."
820 …uction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or…
825 …1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or…
830 …The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss."
835 …": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss."
840 …e processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or…
845 … "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or…
850 … processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss."
855 …rocessor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or…
860 …processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss."
865 …ocessor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or…
870 …nstruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss."
875 …'s L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss."
880 …truction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or…
885 … L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or…
890 …struction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss."
895 …s L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss."
900 …ruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or…
905 …L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or…
910 …uction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss."
915 …1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss."
920 …tion cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or…
925 …data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or…
930 … processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss."
935 …"The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss."
940 …rocessor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or…
945 …he processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or…
950 …: "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss fo…
955 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
960 …: "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or…
965 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
970 …'s instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss fo…
975 …ssor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss fo…
980 …'s instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or…
985 …ssor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or…
990 …ispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss fo…
995 …ispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or…
1000 …data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss fo…
1005 …data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or…
1010 …data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss fo…
1015 …data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or…
1020 …t had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss fo…
1025 …t had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or…
1030 …'s instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss fo…
1035 …ssor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss fo…
1040 …'s instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or…
1045 …ssor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or…
1050 …: "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss fo…
1055 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a …
1060 …: "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or…
1065 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a …
1070 …ispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss fo…
1075 …ispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or…
1080 …data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss fo…
1085 …data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or…
1090 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a …
1095 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a …
1100 …processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss fo…
1105 …The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss fo…
1110 …processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or…
1115 …The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or…
1120 …xclusive) state from another core's L2 on the same chip in the same regent due to a demand miss fo…
1125 …xclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or…
1130 …xclusive) state from another core's L2 on the same chip in the same regent due to a demand miss fo…
1135 …xclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or…
1140 …he was reloaded from another core's L2 on the same chip in the same regent due to a demand miss fo…
1145 …he was reloaded from another core's L2 on the same chip in the same regent due to a demand miss fo…
1150 …he was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or…
1155 …he was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or…
1160 …xclusive) state from another core's L3 on the same chip in the same regent due to a demand miss fo…
1165 …xclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or…
1170 …xclusive) state from another core's L3 on the same chip in the same regent due to a demand miss fo…
1175 …xclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or…
1180 …he was reloaded from another core's L3 on the same chip in the same regent due to a demand miss fo…
1185 …he was reloaded from another core's L3 on the same chip in the same regent due to a demand miss fo…
1190 …he was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or…
1195 …he was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or…
1200 …ve) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss fo…
1205 …ve) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or…
1210 …ve) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss fo…
1215 …ve) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or…
1220 … reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss fo…
1225 … reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss fo…
1230 … reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or…
1235 … reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or…
1240 …usive) state from another core's L2 on the same chip in a different regent due to a demand miss fo…
1245 …usive) state from another core's L2 on the same chip in a different regent due to a demand miss or…
1250 …usive) state from another core's L2 on the same chip in a different regent due to a demand miss fo…
1255 …usive) state from another core's L2 on the same chip in a different regent due to a demand miss or…
1260 …was reloaded from another core's L2 on the same chip in a different regent due to a demand miss fo…
1265 …was reloaded from another core's L2 on the same chip in a different regent due to a demand miss fo…
1270 …was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or…
1275 …was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or…
1280 …usive) state from another core's L3 on the same chip in a different regent due to a demand miss fo…
1285 …usive) state from another core's L3 on the same chip in a different regent due to a demand miss or…
1290 …usive) state from another core's L3 on the same chip in a different regent due to a demand miss fo…
1295 …usive) state from another core's L3 on the same chip in a different regent due to a demand miss or…
1300 …was reloaded from another core's L3 on the same chip in a different regent due to a demand miss fo…
1305 …was reloaded from another core's L3 on the same chip in a different regent due to a demand miss fo…
1310 …was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or…
1315 …was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or…
1320 … state from another core's L2 or L3 on the same chip in a different regent due to a demand miss fo…
1325 … state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or…
1330 … state from another core's L2 or L3 on the same chip in a different regent due to a demand miss fo…
1335 … state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or…
1340 …loaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss fo…
1345 …loaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss fo…
1350 …loaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or…
1355 …loaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or…
1360 …he processor's instruction cache was reloaded from the local chip's memory due to a demand miss fo…
1365 …: "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss fo…
1370 …he processor's instruction cache was reloaded from the local chip's memory due to a demand miss or…
1375 …: "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or…
1380 …rocessor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss fo…
1385 …rocessor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or…
1390 …ocessor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss fo…
1395 …ocessor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or…
1400 …truction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss fo…
1405 … L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss fo…
1410 …truction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or…
1415 … L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or…
1420 …s not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss fo…
1425 …s not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or…
1430 … line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss fo…
1435 … line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or…
1440 …s instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss fo…
1445 …sor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss fo…
1450 …s instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or…
1455 …sor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or…
1460 …s not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss fo…
1465 …s not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or…
1470 … line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss fo…
1475 … line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or…
1480 …s instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss fo…
1485 …sor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss fo…
1490 …s instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or…
1495 …sor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or…
1500 …in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss fo…
1505 …in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or…
1510 …in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss fo…
1515 …in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or…
1520 …ruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss fo…
1525 …L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss fo…
1530 …ruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or…
1535 …L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or…
1540 …he processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss fo…
1545 …: "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss fo…
1550 …he processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or…
1555 …: "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or…
1560 …processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss fo…
1565 …processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or…
1570 …rocessor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss fo…
1575 …rocessor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or…
1580 …struction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss fo…
1585 …s L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss fo…
1590 …struction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or…
1595 …s L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or…
1600 … not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss fo…
1605 … not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or…
1610 …line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss fo…
1615 …line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or…
1620 … instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss fo…
1625 …or's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss fo…
1630 … instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or…
1635 …or's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or…
1640 … not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss fo…
1645 … not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or…
1650 …line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss fo…
1655 …line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or…
1660 … instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss fo…
1665 …or's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss fo…
1670 … instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or…
1675 …or's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or…
1680 …n the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss fo…
1685 …n the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or…
1690 …n the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss fo…
1695 …n the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or…
1700 …uction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss fo…
1705 …1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss fo…
1710 …uction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or…
1715 …1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or…
1720 …e processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss fo…
1725 … "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss fo…
1730 …e processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or…
1735 … "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or…
1740 …rocessor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss fo…
1745 …rocessor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or…
1750 …ocessor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss fo…
1755 …ocessor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or…
1760 …truction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss fo…
1765 … L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss fo…
1770 …truction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or…
1775 … L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or…
1780 …ruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss fo…
1785 …L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss fo…
1790 …ruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or…
1795 …L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or…
1800 …tion cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss fo…
1805 …data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss fo…
1810 …tion cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or…
1815 …data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or…
1820 …rocessor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss fo…
1825 …he processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss fo…
1830 …rocessor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or…
1835 …he processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or…